COL-TSOP with nonconductive material for reducing package...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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Details

C257S676000, C257S686000, C257S692000, C257S701000, C257S783000, C438S123000

Reexamination Certificate

active

07728411

ABSTRACT:
A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.

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patent: 2006/0103012 (2006-05-01), Chin
patent: 2007/0001272 (2007-01-01), Lee et al.
patent: 6-177429 (1994-06-01), None

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