Inductor devices – Coil or coil turn supports or spacers – Printed circuit-type coil
Reexamination Certificate
2002-07-22
2004-04-06
Mai, Anh T. (Department: 2832)
Inductor devices
Coil or coil turn supports or spacers
Printed circuit-type coil
C336S223000, C336S232000
Reexamination Certificate
active
06717503
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a coil and to a coil system for integration into a microelectronic circuit. Furthermore, the invention relates to a microelectronic circuit.
Inductances (coils) are required in a multitude of circuit types, for example in oscillators, amplifiers, mixers or the like. The inductances, i.e., inductors, belong to the component types whose integration on a chip together with the remaining circuit parts can give rise to problems. To date this has meant that inductances are in many cases still used as discrete components, since they would otherwise have disadvantages as coil forms integrated on chips. At very high frequencies, that is to say at frequencies in ranges far above 1 GHz, integrated inductances have to be used in any case since signal transmission then becomes very difficult via the leads of the discrete coils.
FIG. 1
illustrates a typical coil implementation as it is known from the prior art. A metal track runs through a spiral, thereby producing a number of turns with increasing radii. If a plurality of metal layers are available on the chip, such spirals can be stacked. The inductances add up through connection in series. Track resistances are reduced in the event of connection in parallel, which leads to lower power losses. However, these known coils, or coil forms, have a series of disadvantages. A particular disadvantage results, for example, from the punch-through of the magnetic field into the substrate, usually a silicon substrate. Generally, in modern CMOS technologies, a relatively low-impedance substrate is used, which results in a relative high induced current caused by the alternating magnetic fields. This leads to relatively high losses, which means that the quality factor of the integrated inductance (coil) is relatively low. In the gigahertz frequency range, the quality factor is, for example, orders of magnitude lower compared with discrete coils. Since the coil quality factor is an important performance variable of analog circuits, there is a need to improve the quality factor of the coils.
The coil types described above are used in standard CMOS processes, for example. In such processes, a relatively low-impedance substrate is used, which results in the correspondingly low coil quality factors. If a high-impedance substrate is used instead, the losses decrease and the coil quality factor increases. However, a high-impedance substrate can have disadvantageous effects on-an entire series of transistor properties. If high-impedance substrates were used, a standard CMOS process would no longer be possible in any case, and so a different process control would be necessary. However, this is not desirable.
A further possibility for improving the coil quality factor is to remove the substrate material directly below the coil by means of a suitable etching process. A metal layer can then be applied between the coil planes and the substrate. By introducing slots, it is possible to prevent eddy currents, shielding with respect to the substrate being achieved at the same time. However, such a solution has the disadvantage that one metal plane fewer is available for coil turns. Moreover, only slight improvements in the coil quality factor can be achieved therewith.
A further disadvantage of the known coils resides in the relatively large area requirements. The coil geometry shown in
FIG. 1
requires an area of 0.3*0.3 mm at an inductance of approximately 9 nHz. If a larger inductance is required, the area requirement rises proportionally.
European published patent application EP 0 725 407 describes a three-dimensional coil which is integrated in a microelectronic circuit and in which the coil axis lies horizontally with respect to the chip surface. The coil has one or more turns. The turns are produced by interconnects of a lower metalization plane and interconnects of an upper metalization plane and also via contacts connecting them. In general, “via” is understood to mean a connection piece between two metal planes. In the prior art solution, the inductance is achieved by means of a core made of material of high permeability, which core is introduced between the interconnects and via contacts and constitutes a fundamental feature of the prior art solution. In the case of the coil geometry disclosed in EP 0 725 407, only a small part of the magnetic field penetrates into the substrate, with the result that the losses associated with this decrease and, consequently, the quality factor of the coil is improved. Despite this advantage, that coil geometry has not been used to date. This is due, for example, to the fact that a semiconductor-compatible core material is not available at the present time. Moreover, at high frequencies, all materials of high permeability exhibit high magnetization-reversal losses, which in turn limit the coil quality factor. Furthermore, the via resistances are too high in the case of the metalization layers that are typically used.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a coil and a coil system for integration into a microelectronic circuit, and also to provide a microelectronic circuit, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the coils, or coil systems, having a high quality factor can be produced in a simple and cost-effective manner and be integrated into microelectronic circuits.
With the foregoing and other objects in view there is provided, in accordance with the invention, a coil for integration into a microelectronic circuit on a chip, comprising:
interconnects formed in spatially separate metalization planes of the chip;
at least one turn formed by the interconnects, or at least segments of the interconnects, formed in the spatially separate metalization planes; and
via contacts connecting the interconnects and each being formed from a stack of at least two via elements disposed one above the other.
In other words, the first above object is achieved, in accordance with the invention, by a coil for integration into a microelectronic circuit, having one or more turns, the turn(s) being formed by at least segments of two interconnects, which are formed in metalization planes that are in each case spatially separate from one another, and also the via contacts connecting said interconnect(s) and/or interconnect segments. According to the invention, the coil is formed from a stack of two or more via elements arranged one above the other.
This provides a coil having a high quality factor which can readily be integrated into microelectronic circuits. In terms of its basic construction, the coil according to the invention proceeds from the coil described in EP-A-0 725 407. Owing to the low punch-through of leakage fields into the substrate, high coil quality factors can be realized with such a coil geometry. The formula for the inductance in the case of such a coil geometry reads as follows:
L=&mgr;
0
*&mgr;r*A*N
2
/1
In this case, &mgr;0 is the permeability constant (1.2 E
−6
H/M) and &mgr;r is the relative permeability (approximately 100,000 in the case of ferromagnetic material). A is the cross-sectional area of the coil perpendicular to the coil axis, N is the number of turns, and L is the length of the coil. For these reasons described in relation to the prior art, a magnetic core is dispensed with in the case of the coil according to the invention. Instead, it is a basic concept of the present invention that the cross-sectional area of the coil is enlarged. In the case of the solution described in EP-A-0 725 407, this would necessitate very long interconnects in order to realize areas of approximately 10-20 &mgr;m
2
given the thicknesses—customary in standard metalizations—of the via contacts (intermetal dielectrics) of 0.5 &mgr;m to 0.3 &mgr;m. However, these long interconnects have a correspondingly high bulk resistance, as a result of which the quality factor of the coil is reduced. If a higher number of
Berthold Jörg
Sewald Dieter
Tiebout Marc
Greenberg Laurence A.
Infineon - Technologies AG
Mai Anh T.
Mayback Gregory L.
Stemer Werner H.
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