Coherent sampled readout circuit and signal processor for a char

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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307221D, 307353, 328151, 328165, 357 24, H03K 3353, G11C 1928, H04B 104, H01L 2978

Patent

active

RE0300870

ABSTRACT:
A coherent sampled CMOS readout circuit and signal processor coupled to a CCD shift register operated by a two-phase minority carrier transfer clock system. The invention comprises a multiplex MIS switch, a reverse biased collection diode, an N channel MOSFET reset switch, a P channel MOSFET electrometer amplifier, and a sample and hold circuit, the configuration having four distinct operational timing subintervals within a clock period wherein the charge is shifted from one shift register bit to another and finally to the output bit. This removes the Nyquist noise associated with the reset switch, suppresses switching transients and 1/f surface noise to thereby improve the signal to noise ratio, i.e., dynamic range, for a CCD array and readout system.

REFERENCES:
patent: 3537019 (1970-10-01), Reichard
patent: 3720922 (1973-03-01), Kosonocky
patent: 3789312 (1974-01-01), Heller et al.
Kosonocky, "Charge Coupled Digital Circuits" IEEE J. Solid-State Circuits, vol. SC-6 (10/71), pp. 314-322.
Terman, "Charge-Coupled Device Shift Register Read/Write/Regeneration Circuit", IBM Tech. Disclosure Bulletin, vol. 14 (5/72), pp. 3784-3785.
Dennard et al., "Read/Write Amplifier for Charge-Coupled Device Memory", IBM Tech. Disclosure Bulletin, vol. 14 (5/72), pp. 3722-3723.
Dennard, "Regeneration Circuit for Charge-Coupled Device Shift Registers", IBM Tech. Disclosure Bulletin, vol. 14 (5/72), pp. 3791-3792.

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