Coherent PSK demodulator using bit error rate and S/N ratio to e

Details Coherent PSK demodulator using bit error rate and S/N ratio to e Coherent PSK demodulator using bit error rate and S/N ratio to e

1992-01-17

1992-10-20

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 85, 329307, 371 46, H04L 2706

Patent

active

051576945

ABSTRACT:
In a coherent M-ary PSK demodulator, an M-ary PSK detector demodulates a received M-ary PSK modulated convolutional code with a carrier recovered by a voltage-controlled oscillator to produce first and second channels of demodulated convolutional codes. A convolutional decoder decodes the signals of the first and second channels while correcting bit errors. An error rate detector is provided for detecting when the number of such errors occurring during a specified period of time is smaller than a predetermined value and generates a signal indicating that the convolutional decoder is synchronized with the demodulated signals. The power levels of signal and noise components of the demodulated channels are detected by a power detector. In a frequency control circuit, a series of VCO control signals of a different value are generated as candidates for precise synchronization in response to the signal from the error rate detector in order to synchronize the PSK detector successively at the candidate frequencies, and signal-to-noise ratios are successively derived from the outputs of the power detector. A maximum value of the derived signal-to-noise ratios is then detected and one of the candidate VCO control signals which corresponds to the detected maximum signal-to-noise ratio is adopted as a valid VCO control signal.

REFERENCES:
patent: 4726029 (1988-02-01), Motley et al.
patent: 4835790 (1989-05-01), Yoshida et al.
patent: 4837766 (1989-06-01), Yoshida
patent: 4945549 (1990-07-01), Simon et al.

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