Coherent interface with wraparound receive memory

Multiplex communications – Wide area network – Packet switching

Patent

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Details

371 30, H04J 300

Patent

active

046352546

ABSTRACT:
An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes a wraparound receive memory to ensure coherency with very little processor overhead.

REFERENCES:
patent: 4543628 (1985-09-01), Pomfret
patent: 4574375 (1986-03-01), Kemp et al.

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