Coherent interface with wraparound receive and transmit memories

Details Coherent interface with wraparound receive and transmit memories Coherent interface with wraparound receive and transmit memories

1984-12-13

1986-11-18

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 91, H04J 300

Patent

active

046239979

ABSTRACT:
An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes both a wraparound receive and transmit memory to ensure coherency with very little processor overhead.

REFERENCES:
patent: 4205200 (1980-05-01), Parikh et al.
patent: 4227178 (1980-10-01), Gergaud et al.
patent: 4345325 (1982-08-01), Gandini et al.
patent: 4547880 (1985-10-01), DeVita et al.
patent: 4568930 (1986-02-01), Livingston et al.
patent: 4574375 (1986-03-01), Kemp et al.

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