Coherent copyback protocol for multi-level cache memory systems

Details Coherent copyback protocol for multi-level cache memory systems Coherent copyback protocol for multi-level cache memory systems

1996-09-10

1997-09-23

Swann, Tod R.

395473, G06F 1212

Patent

active

056713916

ABSTRACT:
A coherent copyback protocol for a multi-level cache memory system prevents more than one modification from existing in multiple locations and saves access time and data bandwidth. The protocol includes the Latest state. A line in the Latest state has the latest copy of modified data. Additionally, all corresponding lines in any higher cache(s) are marked as invalid and all corresponding lines in any lower level cache(s) are marked as modified.

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"82495DX/82490DX Architectural Overview", Intel, Date Unknown, pp. 18-22.

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