Coherent cache structures and methods

Details Coherent cache structures and methods Coherent cache structures and methods

1988-08-25

1991-07-02

MacDonald, Allen R.

Boots, shoes, and leggings

3642434, 36424341, 364243, 3642281, 3642283, G06F 1208, G06F 1516

Patent

active

050290703

ABSTRACT:
A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis, maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on a time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache having various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occurs, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.

REFERENCES:
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3771137 (1973-11-01), Barner et al.
patent: 4141067 (1979-02-01), McLagan
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4394731 (1983-07-01), Flusche et al.
patent: 4410944 (1983-10-01), Kronies
patent: 4410946 (1983-10-01), Spencer
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4445174 (1984-04-01), Fletcher
patent: 4458310 (1984-07-01), Chang
patent: 4502110 (1985-02-01), Saito
patent: 4607331 (1986-08-01), Goodrich, Jr. et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4631660 (1986-12-01), Woffinden et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4785395 (1988-11-01), Keeley
patent: 4833601 (1989-05-01), Barlow et al.
patent: 4928225 (1990-05-01), McCarthy et al.
Encyclopedia of Computer Science and Engineering, second Edition, 1982, pp. 1409-1413.
"Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model", by J. Archibald, and J. Baer, ACM Transactions on Computer Systems, vol. 4, No. 4, Nov. 1986, pp. 273-298.
"An Economical Solution to the Cache Coherence Problem", by J. Archibald and J. Baer, IEEE, 1984, pp. 355-362.
"Analysis of Multiprocessor Cache Organizations with Alternative Main Memory Update Policies", by W. Yen and K. Fu, IEEE, 1981, pp. 89-101.
"Coherence Problem in a Multicache System", by W. Yen and K. Fu, IEEE, 1982, pp. 332-339.
"A Cache-Based Multiprocessor with High Efficiency", by Michel Dubois, IEEE Transactions on Computers, vol. C-34, No. 10, Oct. 1985, pp. 968-972.
"Effects of Cache Coherency in Multiprocessors", by M. Dubois, and F. Briggs, IEEE, 1982, pp. 299-308.
"Effects of Cache Coherency in Multiprocessors", by M. Dubois and F. Briggs, IEEE Transactions on Computers, Vol. C-31, No. 11, Nov. 1982, pp. 1083-1099.
"The Synapse N+1 System: Architectural Characteristics and Performance Data of a Tightly-Coupled Multiprocessor System", by E. Nestle and A. Inselberg, Synapse Computer Corporation, pp. 233-239, IEEE, 1985.
"Using Cache Memory to Reduce Processor-Memory Traffic", by James Goodman, ACM, 1983, pp. 124-131.
"A New Solution to Coherence Problems in Multicache Systems", by L. Censier, and P. Feautrier, IEEE Transactions on Computers, vol. C-27, No. 12, Dec. 1978, pp. 1112-1118.

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