Coherency and synchronization mechanisms for I/O channel control

Details Coherency and synchronization mechanisms for I/O channel control Coherency and synchronization mechanisms for I/O channel control

1994-10-03

1997-03-18

Auve, Glenn A.

395445, 395462, 395473, 395309, G06F 1200, G06F 1300

Patent

active

056131534

ABSTRACT:
An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide "seamless" I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity.

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