Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2011-03-15
2011-03-15
Thomas, Tom (Department: 2893)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C257SE21521, C257SE21003, C257SE23012
Reexamination Certificate
active
07906374
ABSTRACT:
A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.
REFERENCES:
patent: 2006/0170092 (2006-08-01), Kim et al.
patent: 2004207550 (2004-07-01), None
patent: P2004214430 (2004-07-01), None
patent: 1020060119937 (2006-11-01), None
patent: 2005027221 (2005-03-01), None
Cheng Pai-Sheng
Lin Chiu-Shun
Harrison Monica D
Himax Technologies Limited
Hsu Winston
Margo Scott
Thomas Tom
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