Coefficient storage reduction in adaptive filters in echo cancel

Multiplex communications – Wide area network – Packet switching

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379406, 379410, 379411, 375 11, 375 14, H04J 300

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active

050291670

ABSTRACT:
In an adaptive digital filter for use in an echo canceller or a decision feedback equalizer in a digital data transmission system, reduced storage and lower arithmetic processing speed are attained by subsampling, in effect, the later parts of the waveform, i.e. the tail portion which changes relatively slowly. Such an adaptive digital filter comprises a storage device, such as a shift register, for storing a group of bits which represents symbols being transmitted in the digital data signal, a first stage for deriving an estimate for a first group of the stored bits, and at least one second stage for deriving an estimate for a second group of stored bits occurring earlier in time than the first group. The second stage has a summing device for summing the second group of bits to generate a quantity representing the cumulative sum of the symbols represented in the group, and a multiplier for multiplying the quantity by a single coefficient to obtain an echo estimate for the second stage. The estimates for the first and second echo canceller stages are summed, then subtracted from the received digital data signal. There will usually be a plurality of such second stages, each operative on a different group of bits of the digital data signal.

REFERENCES:
patent: 3978435 (1976-08-01), Luvison et al.
patent: 4605826 (1986-08-01), Kanemasa
patent: 4785445 (1988-11-01), Guidoux
"Mixed Recursive Echo Canceller (MREC)", by C. Mogavero et al., in Proc. Globecom 1986, Dec. 1986, pp. 44-48.
"Architecture for Fully Integrated Echo Canceller LSI based on Digital Signal Processing", by H. Takatori et al., in Proc. ICC 1987, Jun. 1987, 601-605.
A New Digital Echo Canceler for Two-Wire Subscriber Lines, by Nils Holte et al., IEEE Transactions on Communications, vol. Com 29, No. 11-Nov. 1981, pp. 1573-81.

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