Coding rate reduction for turbo codes

Pulse or digital communications – Systems using alternating or pulsating current

Reexamination Certificate

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C714S786000

Reexamination Certificate

active

06628723

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to digital communication and/or storage systems and more particularly to systems and methods for error control.
Error correcting codes insert redundancy into digital information streams to be transmitted or stored so as to reduce their susceptibility to corruption by noise. Applying an error correcting code at the transmitter permits the receiver to detect and sometimes correct errors induced by noise and/or interference. Some popular types of error correcting codes include convolutional codes, block codes, and Reed-Solomon codes, etc.
An important recent development in the topic of error correcting codes is the discovery of “turbo” codes. These codes typically involve an iterated combination of two or more systematic convolutional or block codes (convolutional or block codes where the encoder output bits include unaltered input bits.) A key feature of turbo codes is the use of an iterated decoding technique where each successive decoding step outputs soft decisions useable as input to the next decoding step. By employing turbo codes, one may approach the limit of channel capacity in the presence of noise set by the Shannon theorem.
A part of the appeal of turbo codes is the commercial availability of turbo encoder/decoder integrated circuits. This frees the system designer from concerning himself or herself with most issues regarding the internal operation of the turbo coder or decoder.
Commercially available turbo encoders typically accept as input blocks of data with a limited number of programmable choices of block size. The number of output bits generated for each input block will depend on the input block size and the amount of redundancy added by the encoder. The redundancy added will depend on a programmable parameter known as the encoder rate, the ratio of input bits to output bits. Again, there are typically a limited number of choices of encoder rates.
A problem arises in that is often desirable to more precisely control the number of output bits generated for each input block. For example, in a TDMA (Time Division Multiple Access) system, it is desirable to match the number of bits generated to the size of a single frame. In an OFDM (Orthogonal Frequency Division Multiplexing) system, it is desirable to match the number of bits to be transmitted to the capacity of a single OFDM burst, or an integer number of such bursts. In this way, an optimal number of such frames or bursts can be transmitted without dispersing bits resulting from a single input block over multiple frames or bursts and without wasting capacity that could be used to include redundancy that would provide additional robustness to noise and/or interference.
What is needed is a system for precisely controlling the degree of redundancy introduced by commercially available turbo encoders to facilitate matching output block size to the capacity of a single TDMA frame or OFDM burst.
SUMMARY OF THE INVENTION
Systems and methods for precisely controlling the amount of redundancy introduced by a turbo encoding process are provided by virtue of one embodiment of the present invention. Bits having predetermined values are introduced into the turbo encoding input stream and then deleted from the turbo encoding output stream. At the receiver end, the bits having predetermined values are reintroduced into the encoded information stream as having been received with a maximum confidence level. Coding rate may be varied by varying the number of bits having predetermined values which are inserted at the encoder input. This scheme permits the amount of redundancy to be varied according to system requirements.
A first aspect of the present invention provides apparatus for encoding information prior to transmission. The apparatus includes a systematic coder that receives data bits as input and provides parity bits as output. Selected ones of the data bits are information bits and carry the information while other ones of the data bits are puncture bits and carry predetermined values. The apparatus further includes a connection to a transmitter system that forwards the information bits and parity bits for transmission but not the puncture bits.
A second aspect of the present invention provides apparatus for decoding information after receipt from a transmitter. The apparatus includes a systematic decoder that receives as input estimation information for data bits and parity bits and outputs estimated values for the data bits as corrected by use of the parity bits. The apparatus further includes a receiver system that develops estimation information for the parity bits and selected ones of the data bits based on a received signal, and a puncture reinsertion control block that provides to the turbo decoder estimation information for the parity bits and selected ones of the data bits, and predetermined values for other ones of the data bits.


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Advanced Hardware Architectures, “Turbo Product Codes for LMDS”; 1999 IEEE Radio and Wireless Conference.

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