Coded data generation or conversion – Digital code to digital code converters
Patent
1998-10-26
2000-12-12
Young, Brian
Coded data generation or conversion
Digital code to digital code converters
H03M 700
Patent
active
06160500&
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to processes which make it possible to code special-purpose signal processors. It relates also to signal processors allowing the implementation of such a process.
DISCUSSION OF THE BACKGROUND
It is known that apart from processors of a general type such as those used for example in personal computers, there are special-purpose processors, especially those intended for processing signals whose structure is especially adapted to the simultaneous execution of several activities. The activities are systematic and involve access to the memories, calculations on data and management of the number of iterations.
By way of example of such a processor mention will be made of those manufactured by the company Analog Device under the references 21020 or 21060.
By referring to the technical handsheet for such a processor, it may be observed that the processing of the data is carried out essentially by repeating two types of elementary actions. One of these actions consists in successively obtaining a certain number of addresses in the memory by using a data address generator (DAG). The other of these actions consists in performing a particular processing operation on the data thus selected and in iterating this processing operation a specified number of times with the aid of a repetition counter (loop count stack). The generating of the addresses and the management of the length of the loop are determined by programming. The programming of these two actions is done separately and the relations between the two are determined by the human programmer, who devises the programs by making a mental note of the necessary relations. There is therefore no automatic aspect and a risk of errors exists.
The inventor has already developed a signal processing application graphical input process making it possible to formalize the signal processing applied to such signals by presenting them in the form of input and output arrays and by establishing systematic relations between these arrays.
This formalism leads to the development of a special-purpose signal processor enabling it to be implemented directly. This graphical input process has formed the subject of a French Patent Application filed by the Applicant on Apr. 7, 1995 under No. 95 04175.
The formalism in question has also formed the subject of a paper at the 1995 GRETSI colloquium at JUAN LES PINS, FRANCE.
Finally, it is planned to present this formalism, as well as programming tools, on the Internet from the University of Berkeley server at the address:
http://ptolemy.eecs.berkeley.edu.
This formalism, which can also be regarded as a language, is known in the art by the name ARRAY-OL.
In the framework of these studies, the inventors have also invented a coding process making it possible to unify the two repetitive actions described above, so as automatically to have the desired result without being obliged to link the two operations mentally at programming level.
SUMMARY OF THE INVENTION
To do this, the invention proposes a coding process for a signal processor, which starts from an input array which is sampled with an input pattern according to an input assembling relation and an input paving relation, each of these patterns is subjected to an elementary transformation TE which delivers output patterns, and an output array is constructed by assembling these output patterns according to an output paving relation and an output fitting relation, principally characterized in that a first output multidimensional space is determined, comprising a first set of axes corresponding to the axes of the quotient array resulting from dividing the output array by the output pattern itself regarded as an output divisor array, and a second set of axes corresponding to the axes of this output divisor array, this first space thus comprising all the outputs of the output array arranged in such a way as to be able to be traversed successively by an incrementation of the clock of the processor, and in that
REFERENCES:
patent: 4542455 (1985-09-01), Demeure
patent: 4604736 (1986-08-01), Demeure
patent: 4661957 (1987-04-01), Okuhara
patent: 5715216 (1998-02-01), Dang et al.
"Thomson-CSF"
Young Brian
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