Coding method of multi-level memory cell

Details Coding method of multi-level memory cell Coding method of multi-level memory cell

2002-04-03

2004-06-29

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185090, C365S185240, C365S185330, C365S185040

Reexamination Certificate

active

06757193

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90113161, filed May 31, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a coding method for a data storage medium, and more particularly, to a coding method of a multi-level memory cell.
2. Description of the Related Art
Multi-level memory cell is a kind of memory cell that comprises n (N>1) bits and has 2
n
levels to store one of 2
n
codes. Each code is formed with n bits. The value of the 2
n
codes is 0 to 2
n−
1. “Multi-level” means that the memory cell can have multiple threshold voltages V
T
. For a certain kind of multi-level memory cell, the threshold voltage is set as one of the 2
n
levels for programming. The threshold voltage is then used to determine the stored code for reading. This kind of multi-level memory cell includes electrically erasable programmable read only memory (EEPROM) or mask read only memory (Mask ROM). On the other hand, for the multi-level memory cell in the dynamic random access memory (DRAM), the gate voltage is set to 2
n
V
T
, SO that the capacitor has a certain voltage, and the certain voltage is retrospectively referred to obtain the stored data for reading.
The conventional coding method of a multi-level memory cell is to arrange according to the values of 2
n
codes, and then correspond to each level from low to high sequentially. In
FIG. 1
, a multi-level memory cell with 2 bits is used as an example. In the conventional method, the codes are (11), (10), (01) and (00) with respect to the first to the fourth levels from low to high. In
FIG. 2
, a multi-level memory cell with 3 bits is used as an example. The codes are (111), (110), (101), (100), (011), (010), (001) and (000) with respect to the first level
201
to the eighth levels
208
, from low to high.
Although the multi-level memory cell can store massive amounts of information, the large number of levels causes errors of storing another code of the level before or after the exact level of which a specified code is to be stored. Thus, the error code correction (ECC) is very important. Such error code correction compares the actual storage value to the predetermined storage value after programming the memory cell. The error address of the memory cell and the bit record requiring correction are saved into an additional memory cell.
A common error code correction rule includes a 2
q
+2q−1 rule. That is, 2q−1 additional spaces are given to store the error code correction data in each 2
q
bits of data of a memory, whereas, 2q−2 bits are used to stored the address of the error memory cells and the remaining one bit is used to store the corrected bit. When the probability of the error occurrence for data storage is high, the value of q has to be reduced to increase the proportion of the error code correction memory cells ((2q−1)/2
q
). That is, with the same data storage spaces, more additional spaces are consumed to store error data, and vice versa.
In
FIG. 1
, in the conventional coding method of a 2 bit multi-level memory cell, the bit difference between two codes of two neighboring levels is 1, 2, 1, sequentially. That is, if one mistakenly writes (01) as (10) or (10) as (01), the corrected bit number to be stored is 2. Referring to
FIG. 2
, in the conventional coding method of a 3 bit multi-level memory cell, the bit difference between two codes of two neighboring levels is 1, 2, 1, 3, 1, 2, 1 in sequence. The corrected bit number is even more. In the conventional coding method, more than one error bits are generated when one memory cell is wrongly written. More storage spaces of the memory are thus consumed.
SUMMARY OF THE INVENTION
The invention provides a coding method of a multi-level memory cell applied to a programming operation of a multi-level memory cell. The multi-level memory cell can store n bits and has 2
n
levels with respect to 2
n
codes. Each code comprises n bits. In the coding method, a code to be stored is provided. According to a relationship between the code and level, a specified level of the code to be stored is obtained by the multi-level memory cell. The relationship between the code and the level is a correspondence between the 2
n
codes and the 2
n
levels. Two codes of any two corresponding neighboring levels have a one bit difference.
In the above coding method of multi-level memory cell, the range of n is 2≦n≦4.
The invention further provides a programming method of a multi-level memory cell. Data is written to a multi-level memory cell using the above coding method. An error code inspection step is performed. If the actual stored code of any memory cell has one bit different from the predetermined stored code, the address of this multi-level memory cell and the different bit are written into an additional error code correction memory cell.
As mentioned above, since two codes of two neighboring levels only have one bit difference, whatever n is, when a specified code of a corresponding level is mistakenly written as another code of the level right before or after such certain level, only one additional correction bit is required. The number for a correction bit is thus decreased, and the space occupied by storing the correction bit is saved.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 6262913 (2001-07-01), Hutchison
patent: 6266270 (2001-07-01), Nobukata
patent: 6400601 (2002-06-01), Sudo et al.
patent: 6560143 (2003-05-01), Conley et al.

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