Coding/decoding system of bit insertion/manipulation line...

Coded data generation or conversion – Digital code to digital code converters – To or from minimum d.c. level codes

Reexamination Certificate

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C341S056000

Reexamination Certificate

active

06333704

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a coding/decoding system of bit insertion/manipulation line code for a high-speed optical transmission system. More particularly, it relates to a coding/decoding of bit insertion/manipulation (BIM) line code for a high-speed optical transmission system using AC coupling, which keeps a running digital sum (RDS), essential for transmission of binary data at a high-speed, zero, and minimizes the digital sum variation with simple configuration.
2. Description of the Related Art
Except that line codes used in the general optical transmission system use only codes of low levels due to the optical device characteristics, they have the requirements similar to those used in the following conventional transmission system using AC coupling.
First, the conventional transmission system must have bit sequence independence. Second, the fluctuation of the DC baseline of the bit stream should be minimized to be neglected at its receiving part. Third, the system must have the in-service error monitoring capability of detecting transmission errors even during data transmission. Fourth, sufficient bit transitions in the codeword must be guaranteed for the timing extraction at the receiving part. Fifth, if the structures of encoder/decoder are not simple, it is difficult to provide the required transmission performance at high-speed and increases the overall costs. Therefore, the system should be realized in a simple hardware.
Sixth, minimizing an increase in bit rate is very important in the high-speed transmission system, and that is because the increase in bit rate raises the operation clock rate, thus making it difficult to realize an electronic circuit in high-speed application. Seventh, the case where there are the same consecutive bits (i.e. consecutive ‘0’ or ‘1’) in a bit stream also causes a limit to the system performance, and that is because the long continuity of the same bits makes it difficult to extract timing information and causes the DC baseline fluctuation.
Conventionally, a method of using a codeword with a bit rate twice as high as the information data's as a transmission code in order to transmit binary data (disclosed in [AMI: Barker R. H, B.P. 706,687], [CMI: CCITT Rec. G. 722], [Manchester:IEEE 802.3 Ethernet], etc.) has been employed. This method assures the BSI and DC balance and easily extracts clock component from the bit stream. However, this method should generate a codeword having bit rate twice as high as the information data's. Thus, it is not suitable for the applications having high bit rate such as high-speed optical transmission system since it is difficult to realize the system employing electronic circuits in a small size, low power consumption and requires a lot of cost.
In order to solve the above problem, in 1960's, mBnB (m=natural number, m2, n3) line code that satisfies the DC balance and minimizes an increase in bit rate was proposed. (4B5B, 5B6B [R. Petrovic, Electronic Letters, 1988, Vol. 24, No. 5, pp274 to 275] in FDDI, 8B10B in Fibre Channel, etc.). However, this method adopts the lookup table using a read only memory (ROM) in order to convert the m-bit information data into n-bit codewords with DC balance, resulting in restricted data transmission speed due to the ROM with relatively low operating speed. Even if the ROM is not used, the larger the value m becomes, the more complicated an encoder/decoder circuit becomes whereby a high-speed electronic circuit cannot be realized.
In the 1980's, there was proposed a method using a bit insertion code that inserts 1-bit indication bit into m-bit information data to minimize the increase in bit rate for the high-speed optical transmission of data of more than several hundred megabits and simplifies the configuration of the encoder/decoder ([mB1C: IEEE Tran. COM, Vol. COM-32, No. 2, pp 163 to 168, 1984, Moriaki Yoshikai, et al], [DmB1M: IEEE J. on SAC, Vol. SAC-4, No. 9, pp. 1432 to 1437, 1986, Moriaki Yoshikai et al], [PFmB(m+1): IEEE Tran. COM, Vol. COM-37, No. 4, pp. 402 to 404, 1989, Witold A. Krzymien], [U.S. Pat. No. 5,200,979 High Speed Telecommunication System using a novel line code, 1993, Gwendolya K. Harris]. As an example of this method, the mB1C code simplifies the structure of the encoder/decoder by inserting a complementary 1 bit of the least significant bit of the information data into the information data. In addition, it produces at least one bit transition at every m bit to facilitate the clock extraction at the receiving part but the DC balance is not guaranteed.
In order to obviate the above problems, there has been developed DmB1M code obtained by inserting the insertion code and then exclusive-Oring information bits by bit to have average DC balance.
PFmB(m+1) code was developed to more compensate the DC balance problem. The PFmB(m+1) code is created by inserting bits minimizing the DC balance of the information data and performing pre-coding. With the PFmB(m+1) code, in order to minimize the DC balance, ‘0’ is inserted if the polarity of disparity of the information data is positive (+), and ‘1’ is inserted if it is negative (1). The polarity of the information data pre-coded as above is compared with the polarity of data accumulated during transmission, and, if they are opposite to each other, the information data is transmitted without any change, but if they are identical to each other, the information data is inverted to be transmitted, thereby maintaining the overall DC balance.
However, though the bit insertion method has a small increase in bit rate and a simple mechanism compared to the mBnB code, it has big DC baseline fluctuations by maintaining at most the average DC balance.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a encoding/decoding apparatuses according to bit insertion/manipulation for a high-speed optical transmission system, which minimizes DC baseline fluctuations with a small bit increase rate and simple mechanism by properly coupling advantages of the conventional mBnB line code and bit insertion code.
In order to achieve the above object of the present invention, the present invention provides a encoding/decoding system of bit insertion/manipulation line code, which includes an encoding part of converting information data into codewords, and a decoding part of recovering the codewords received through a transmission path into the information data. The encoding part inserts a bit for minimizing a disparity of m+1 bit block when a disparity of m-bit input information is a minimum value that the m-bit block may have, and inserts ‘0’ when it is not, to perform pre-coding. Then, the encoding part manipulates a part of the bits of the pre-coded block to make its disparity have the minimum value, and compares the disparity of the pre-coded block with a disparity value accumulated, and inverts or non-inverts the block, thus performing coding. The decoding part removes the insertion bit from the coded information, inverts the block again when it is inverted during encoding, and carries out manipulation opposite to the bit manipulation, thus executing decoding.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4309694 (1982-01-01), Henry
patent: 4620311 (1986-10-01), Immink
patent: 5012240 (1991-04-01), Takahashi et al.
patent: 5022

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