Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-12-22
2003-06-24
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S498000, C370S503000, C370S529000, C370S535000, C370S536000, C370S542000, C348S512000, C382S232000
Reexamination Certificate
active
06584125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a coding/decoding apparatus, a coding/decoding system and a multiplexed bit stream and particularly, to a system for synchronously combining and reproducing natural pictures, voices, and computer graphics.
2. Description of the Related Art
MPEG (Motion Picture Coding Expert Group) has been known as an international standard for coding standardization for compressing, multiplexing and transferring or storing audio signal (or voice signal), video signal, and artificial scene data such as computer graphic, and then separating and expanding the signals and data to obtain original signals. The MPEG is defined by the working group (WG)
11
within SC29 which are managed under JTC1 (Joint Technical Committee
1
) for handling common items in data processing fields of ISO (International Organization for Standardization) and IEC (International Electrotechnical Commission). In the MPEG, a mechanism for synchronously reproducing each media from multiplexed data is described.
First, a mechanism for synchronously reproducing an audio signal and a video signal from multiplexed data is described in ISO/IEC 13818-1 “Information Technology Generic Coding of Moving Pictures and Associated Audio Systems” (popularly called MPEG-2 Systems).
FIG. 53
of the accompanying drawings shows the construction of a fixed delay model used for the description. This figure shows an abstracted system architecture when MPEG-2 is applied to compress audio signals and video signals.
In
FIG. 53
, encoder
71
compresses (encodes) audio signal, and encoder
72
compresses (encodes) video signal. Buffer
73
buffers the audio data compressed by the encoder
71
, and buffer
74
buffers the video data thus compressed by the encoder
72
. Multiplexing circuit
75
multiplexes the compressed audio data LO stored in the buffer
73
and compressed video data stored in the buffer
74
. At this time, a reference clock that is needed for synchronous reproduction and time stamps are embedded as additive information into the multiplexed data.
Specifically, the time stamps are a decoding time stamp representing a decoding timing and a display time stamp representing a display timing. The decoding time stamp is generally used only when interpolative prediction is carried out. This is because when the interpolative prediction is carried out, the decoding timing and the display timing are different from each other in some cases. In the other cases, the decoding time stamp is unnecessary.
Storage/transmission device
76
stores or transmits the multiplexed data created by the multiplexing circuit
75
. Separation circuit (demultiplexing circuit)
77
separates compressed audio data, compressed video data, and a reference clock and time stamp used for synchronous reproduction from the multiplexed data supplied from the storage/transmission device
76
. Buffer
78
buffers the compressed audio data supplied from the separation circuit
77
, and buffer
79
buffers the compressed video data supplied from the separation circuit
77
. Decoder
80
decodes and reproduces the compressed audio data stored in the buffer
78
, and decoder
81
decodes and displays the compressed video data stored in the buffer
79
.
The synchronous reproduction of the audio signals and video signals in
FIG. 53
is implemented as follows. The reference clock embedded in the multiplexed data is used to control the oscillation frequency of a clock generating circuit for driving the decoder
80
and decoder
81
, and PLL (Phased Locked Loop) is generally used. The synchronization between the encoder side and the decoder side is established by the PLL. The time stamp embedded in the multiplexed data is used to transmit the decoding timing of the decoder
80
and decoder
81
or the reproduction/display timing of the decoding result. The time axes of the encoder side and decoder side are synchronized with each other with a fixed delay being set therebetween by the reference clock, and the decoding operation is started at the time which is intended at the encoder side and the reproduction/display is carried out.
Accordingly, the synchronous reproduction of the audio signals and video signals can be implemented insofar as a suitable time stamp is set at the encoder side. In the case of an application in which synchronous reproduction isn't needed between the encoder side and the decoder side, the synchronous reproduction is carried out with the clock of the decoder itself without using the reference clock.
Next, ISO/IEC JTC1/SC29/WG11 N1825 “Working Draft 5.0 of ISO/IEC 14996-1” (popularly called MPEG-4 Systems) describes a mechanism for synchronously reproducing audio signals, video signals, and artificial scene data such as computer graphics from multiplexed data.
FIG. 54
shows a system decoder model (SDM) used for the description of the above mechanism. This model is an abstracted system decoder when MPEG-4 is applied to compress audio signals, video signals, and artificial scene data such as computer graphics. In this paper, detailed description isn't made on the model and concrete construction of the encoder, however, it is described as syntax that a reference clock and a time stamp are embedded as additive information in multiplexed data. Specifically, there are provided two time stamps, a decoding time stamp representing a decoding timing and a composite time stamp representing a timing at which decoded data can be supplied to a composition circuit.
In
FIG. 54
, a separation circuit
91
separates from the multiplexed data compressed audio data, compressed video data, compressed scene data, and a reference clock and a time stamp used for synchronous reproduction. Buffer
92
buffers the compressed audio data supplied from the separation circuit
91
, and buffer
93
buffers the compressed video data supplied from the separation circuit
91
. Buffer
94
buffers the compressed artificial scene data supplied from the separation circuit
91
. Decoder
95
decodes the compressed audio data stored in the buffer
92
, decoder
96
decodes the compressed video data stored in the buffer
93
, and decoder
97
decodes the compressed artificial scene data stored in the buffer
94
.
Buffer
98
buffers the audio signal decoded by the decoder
95
, buffer
99
buffers the video signal decoded by the decoder
96
, and buffer
100
buffers the artificial scene data decoded by the decoder
97
. Composition circuit
101
composes a scene on the basis of the audio signal stored in the buffer
98
, the video signal stored in the buffer
99
and the artificial scene data stored in the buffer
100
. At this time, the scene information that is composed is described in the artificial scene data, and in accordance with the scene information the audio signal is modulated or the video signal is deformed, and the signal is mapped to an object in the scene. Display circuit
102
reproduces/displays a scene supplied from the composition circuit
101
.
The composition and reproduction of the audio signal, the video signal and the artificial scene data in
FIG. 54
is implemented as follows:
The reference clock can be provided every decoder. After it is picked up from the multiplexed data, it is input to a clock generating circuit which is provided every decoder in order to control the oscillation frequency of the clock generating circuit, whereby the synchronization between the encoder side and the decoder side can be established every decoder. The time stamp can be also provided every decoder. After it is picked up from the multiplexed data, it is used to transmit the time at which the decoding timing of the decoder or the decoding result can be supplied to the composition circuit
101
. The time axes of the encoder side and the decoder side are synchronized with each other with a fixed delay being set therebetween by the reference clock, and the decoding is started at the time intended by the encoder side and the writing operation into the buffer is carried out.
Subsequently, the comp
Kizou Hassan
Logsdon Joe
LandOfFree
Coding/decoding apparatus, coding/decoding system and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Coding/decoding apparatus, coding/decoding system and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coding/decoding apparatus, coding/decoding system and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3088555