Coding/decoding apparatus and coding/decoding method

Image analysis – Image compression or coding – Parallel coding architecture

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352247, 3582612, 3582614, 358430, H04N 1417

Patent

active

058481940

ABSTRACT:
Address information generated and output by an address converter for each pixel of input image data in accordance with the phase based on the position of the pixel to be coded is stored in an address storage divided into address groups which are periodically referred to. Information indicative of the occurrence probability of the pixel to be coded and phase information of the pixel are selectively output from the address storage, and an arithmetic coding is performed for the output. During the processing, update data is written in to one group while a read-out is being performed for the other group. A template is constituted by excluding a pixel which predeses one pixel, and a prediction state in each phase is divided into two parts. The template output is applied to both of the divided storage devices, and read actions are independently performed.

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