Coding and modulation method and apparatus for its...

Pulse or digital communications – Systems using alternating or pulsating current – Plural channels for transmission of a single pulse train

Reexamination Certificate

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C375S264000, C714S790000

Reexamination Certificate

active

06704368

ABSTRACT:

TECHNOLOGICAL FIELD
The invention relates to combining coding and modulation that are used to handle a digital signal for high-frequency transmission in a noisy channel.
BACKGROUND OF THE INVENTION
In an attempt to increase the communication speed of digital radio systems, binary signals have been replaced by multiple-valued signals in connection with a high-level modulation scheme. Here we consider 16-QAM ( 16-level Quadrature Amplitude Modulation) as an example of high-level modulation. Multiple-valued signals require the signal encoder and decoder to have special properties.
FIG. 1
illustrates a multi-level encoding and decoding arrangement known from the document “H. Imai, S. Hirakawa: A New Multilevel Coding Method Using Error-Correcting Codes, IEEE Transactions on Information Theory, Vol. IT-23, No. 3, 1977”, which is incorporated herein by reference. Encoder
100
consists of a serial/parallel conversion circuit
101
, M parallel binary encoders
102
-
105
, where M is a positive integer (here M=4), and a mapping circuit
106
. The output signal of the encoder
100
travels through a channel
107
and reaches a decoder
108
including a demultiplexing decoding circuit
109
, which produces M parallel signal estimates, and a selection circuit
110
, which reconstructs the original information from the estimates at its input. Modulation and demodulation are included in the channel part
107
of FIG.
1
.
The serial/parallel conversion circuit
101
converts a stream of binary symbols into M component streams which may have different rates. Each component stream is fed into its own binary encoder
102
-
105
. The generic definition of a multi-level encoder sets very few specific requirements to the parallel binary encoders
102
-
105
, although in many cases they are selected to produce a coded data stream of equal rate. The mapping circuit
106
reads bits from the output of each binary encoder and maps these bits into a corresponding multi-level signal, which has one of the 2
M
allowed levels or states. Especially in the case of 2
M
-order QAM modulation M must be even and the output states of the mapping circuit
106
correspond to the allowed phase and amplitude value combinations of an oscillating signal.
FIG. 3
illustrates a so-called multi-stage decoder
300
that can be used as the decoder
108
in the arrangement of FIG.
1
. At each sampling moment the input signal in line
301
is supposed to be in one of the 2
M
allowed states. The first metric block
302
produces a metric or a probability value that indicates, whether the least significant bit describing the state of the input signal should be 0 or 1. A decision of the corresponding decoded bit value is made in the first decoder
306
. At each further horizontal level of the multi-stage decoder one of the decoders
307
-
309
makes a further decision, and each of the encoders
310
-
312
provides the respective decision in re-encoded form as an additional input to the metric block
303
-
305
of the remaining levels. Delay elements
314
-
319
take care of the mutual timing of the signal parts before and after decoding, so that after the last decision about the decoded bit value is made in block
309
, multiplexer
320
may construct the original bit stream from the outputs of delay elements
317
-
319
and decoder
309
in a way that is reciprocal to the operation of the serial/parallel conversion circuit
101
in the transmitter (see FIG.
1
).
If the computational capacity of the receiving device is high enough with respect to the rate of the incoming received signal, a feedback connection could be arranged from decoder
309
to the first metric block
302
through an additional encoder. The resulting device would be capable of so-called iterative decoding, where the first round of decisions in the decoder blocks
306
to
309
serves as an input to a second (iterative) round and so on. The more iterations on each symbol, the smaller the chance of an erroneous decoding decision.
The problem of a conventional MLC-MSD arrangement (Multi-Level Coding-Multi-Stage Decoding) is its inflexibility with respect to varying rates of coding. A radio channel is prone to fluctuating noise and interference, so different coding rates are required at different times. If the radio capacity (in terms of frequency and time) allocated to a certain radio connection is fixed and interference conditions suddenly get worse, it may be necessary to increase the amount of coding and decrease the effective data rate correspondingly to get even some data through to the receiving station. Similarly if the interference eases off, the transmitting device may use the chance to reduce coding, thereby increasing the effective data rate. This approach is naturally applicable to non-real time connections (so-called non-transparent data services) only, where a fixed data rate is not required. However, the radio system may allow the radio capacity allocations of separate connections to vary, whereby a real-time connection (transparent data services) can sustain its fixed data rate at all times and simultaneously fight interference with a variable coding rate together with a variable amount of reserved radio capacity. In any case it may be necessary to have a maximum coding rate close to 1 (exactly 1 means that no redundancy is added by coding) and a minimum coding rate as low as 0.1 (meaning that ten coded bits are transmitted per each data bit), and the possibility of choosing more or less freely therebetween according to need.
A conventional approach to enable a selection of coding rates is known from the publication “EDGE Feasibility Studies, Work Item 184: Improved Data Rates through Optimised Modulation; ETSI STC SMG 2, Munich, Germany, May 12-16, 1997”, which is incorporated herein by reference. This approach for transparent data services is illustrated in
FIG. 4
b,
where data bits are input into block
401
and coded symbols are output from block
410
. Blocks
401
to
405
form a so-called concatenated encoder, where block
401
first maps the data bits into preliminary symbols, block
402
performs RS (Reed-Solomon) encoding on those, block
403
interleaves the RS-coded preliminary symbols within a selectable interleaving length N1 and block
404
maps the result again into bits. A fixed-rate convolutional encoder
405
with codingrate ⅓ adds redundancy to the bit stream. The serial to parallel converter
406
sends groups of four consecutive bits in parallel into puncturing blocks
407
a
and
407
b
and after that an additional interleaver
408
performs bit interleaving over an interleaving period of four frames. Further serial to parallel converters
409
a
and
409
b
are used to feed the four manipulated parallel bit streams into a Q-O-QAM mapper
410
which operates according to a so-called Gray mapping to produce the output symbols.
FIG. 4
b
illustrates a corresponding approach for non-transparent data services, where the RS encoder
402
has been replaced with a simple CRC (Cyclic Redundancy Check) encoder
402
′ which adds to the bit stream a CRC checksum at predetermined intervals called frames. The purpose of a CRC checksum in each frame is not to correct errors in received frames but to detect them so that the receiving device may ask for a retransmission of a defective frame. Because the CRC calculation takes place on bit level, the conversion blocks
401
and
404
of
FIG. 4
a
may be omitted and the interleaver block
403
′ operates on bits and not preliminary symbols like block
403
in
FIG. 4
a.
One of the drawbacks of the prior art arrangements of
FIGS. 4
a
and
4
b
is that iterative decoding and Multi-Stage Decoding cannot be used as the decoding method, which impairs the performance of the system in comparison with the theoretical optimum. Another drawback is that to meet the ETSI standards (European Telecommunications Standards Institute) for real-time (transparent) data services, the concatenated codes used in blocks
402
and
405
must be rather complicated. Additionall

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