Coder/decoder for time compressed integration system

Details Coder/decoder for time compressed integration system Coder/decoder for time compressed integration system

1988-01-20

1989-08-15

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358330, 358 11, 358 21R, H04N 712, H04N 1120, H04N 979

Patent

active

048580040

ABSTRACT:
A coder/decoder for a time compressed integration system includes a coder for performing time compressed ingtegration of compressed wide- and narrow-width chrominance signals and a luminance signal having passed through a first phase compensation delay circuit and outputting a time compressed integration (TCI) signal, and a decoder for decoding the luminance signal and the chrominance signals from the TCI signal. The coder and the decoder are substantially arranged on a single LSI chip. The coder/decoder includes a first and a second memory section. In a coder mode, the first memory section serves as the first phase compensation delay circuit and part of the second memory section serves as the tapped delay devices in the vertical filters. In a decoder mode, the first memory section and one part of the second memory section serve as a second phase compensation delay circuit, and the other part of the second memory section serves as a tapped delay device in an interpolation filter.

REFERENCES:
patent: 4630099 (1986-12-01), Rzeszewski
patent: 4652903 (1987-03-01), Lucas
patent: 4677498 (1987-06-01), Tsushima
patent: 4692801 (1987-09-01), Ninomiya et al.
patent: 4710810 (1987-12-01), Koga
patent: 4739390 (1988-04-01), Achiha et al.
patent: 4745459 (1988-05-01), Ninomiya et al.

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