Coded incrementer having minimal carry propagation delay

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377 44, 377 46, 377 54, 377 78, 377126, 364900, 3649602, 3649606, 3649265, G06F 750

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049146165

ABSTRACT:
As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.

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G. Williams--"Digital Technology", Science Research Associates--1977, 1982--pp. 283-285.
Computer System Architecture, pp. 54-59, M. Morris Mano, 1982, Prentice-Hall, Inc.

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