Coded decimal non-restoring divider

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364762, 364766, G06F 752

Patent

active

046928910

ABSTRACT:
This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.
A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.
The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

REFERENCES:
patent: 3735108 (1973-05-01), Bolt et al.
patent: 4466077 (1984-08-01), Iannucci et al.
patent: 4603397 (1986-07-01), Ohtsuki et al.
Markin, "Implementation of Division Algorithm Halves Iteration Time" Computer Design Jul. 1979, pp. 129-134.
Lemaire et al., Improved Non-Restoring Division" IBM Tech. Disclosure Bulletin, vol. 23, No. 3, Aug. 1980, pp. 1149-1151.

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