Codec having controllable frame synchronizing and clocking signa

Details Codec having controllable frame synchronizing and clocking signa Codec having controllable frame synchronizing and clocking signa

1992-01-21

1993-10-12

Pellinen, A. D.

Coded data generation or conversion

Reversible analog to digital converters

H03M 102

Patent

active

052529720

ABSTRACT:
A codec comprises a control circuit for generating a frame synchronous signal and a clock signal which are controlled to comply with different types of data carried on a received digital signal to be converted to a received analog signal in a decoder and data carried on a transmitting digital signal converted from a transmitting analog signal.

REFERENCES:
patent: 4160243 (1979-07-01), Moriya et al.
patent: 4348768 (1982-09-01), Svala
patent: 5127023 (1992-06-01), Tash et al.

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