CODEC for consecutively performing a plurality of algorithms

Details CODEC for consecutively performing a plurality of algorithms CODEC for consecutively performing a plurality of algorithms

1999-02-25

2001-03-13

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Coding by table look-up techniques

C341S155000, C712S228000, C712S246000, C709S241000

Reexamination Certificate

active

06201488

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CODEC and, more particularly, to a CODEC having a DSP which can perform a plurality of algorithm processes.
2. Description of the Related Art
In recent years, with the development of communication networks, a CODEC (coder and decoder) having a larger capacity has been required.
Conventionally, a CODEC has a DSP (digital signal processor) therein so as to encode and decode a digital signal by the DSP.
FIG. 1
is a block diagram of a conventional mask-type DSP. The DSP
200
shown in
FIG. 1
comprises a ROM
201
, a RAM
202
, an IO port
203
and a DSP core
204
. The ROM
201
stores programs for operations of the DSP
200
. The RAM
202
stores working data. Data is input from or output to an external device via the IO port
203
. The DSP core
204
executes programs loaded from the ROM
201
by using the work data received from the RAM
202
. The DSP core
204
has a program counter (PC)
205
which serves as an access pointer of the ROM
201
.
When the DSP
200
is in operation, programs stored in the ROM
201
are sequentially read by the DSP core
204
in an order starting from an address designated by the PC
205
, and the read programs are executed by the DSP core
204
. A result of execution of the programs is output from the IO port
203
. Additionally, when the DSP
200
is in operation, the work data stored in the RAM
202
is read by the DSP core
204
, if necessary, and the read work data is processed by the DSP core
204
. The processed work data is stored in the RAM
202
.
As mentioned above, since the programs and the work data are separately stored in different memories, the DSP can perform a high-speed processing.
FIG. 2
is a block diagram of the DSP
200
shown in
FIG. 1
in a state in which a signal having two channels is processed. As shown in
FIG. 2
, the RAM
202
has tow independent memory areas so as to process the signal having two channels. One of the two memory areas stores work data for a channel (1) and the other stores work data for a channel (2). By structuring the RAM
202
as mentioned above, programs in the ROM
201
are executed twice within a unit time so as to achieve a processing of the signal having the two channels.
The above description is for a case in which an algorithm (programs) of each channel is the same. Conventionally, when a plurality of algorithms are required, a plurality of CODECs each of which processes according to only one specific algorithm are provided. Accordingly, in the conventional system, algorithms to be executed cannot be changed in response to a dynamic change in network traffic.
In order to change algorithms in response to a dynamic change in network traffic, a plurality of algorithms must be stored in a single CODEC. However, a memory provided in a DSP of a conventional CODEC does not have a capacity sufficient for storing programs for executing a plurality of algorithms. Accordingly, when the conventional DSP executes an algorithm different from an algorithm being executed, there is a problem in that an execution of a current program must be temporarily stopped so as to load other programs to the memory in the DSP.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful CODEC in which the above-mentioned problem is eliminated.
A more specific object of the present invention is to provide a CODEC having a DSP which can consecutively execute a plurality of algorithms without restriction of a memory capacity.
In order to achieve the above-mentioned objects, there is provided according to the present invention a CODEC comprising a data processing unit performing an encoding/decoding operation on a digital signal, the data processing unit comprising:
a program memory storing a program divided into a plurality of block programs, the program being stored on an individual block program basis;
a data memory storing a set of data used for executing each block program stored in the program memory, the set of data being divided into a plurality of data blocks and stored on an individual data block basis;
a program executing unit executing each block program stored in the program memory by using a corresponding data block stored in the data memory; and
a program changing unit obtaining a new block program from an external device each time execution of one of the block programs by the program executing unit is completed so as to store the obtained new block program in the program memory.
According to the present invention, the program changing unit loads the new block program provided from the external device to program memory at a timing of completion of execution of one of the block programs. Thus, each of the block programs in the program memory is executed in each phase, and a program can be provided from an external device and is stored in the program memory on an individual block basis. Accordingly, a plurality of programs (algorithms) can be consecutively performed when the CODEC is operated over a plurality of phases.
The phase means a time period during which the CODEC executes a single program, and is equalized. For example, a plurality of algorithms can be performed by executing a program A in phase 1, program B in phase 2 and program C in phase 3.
Additionally, a program having a large amount which exceeds a capacity of the program memory can be executed by dividing the program into a plurality of block programs and executing each of the block programs by sequentially loading each of the block programs to the program memory.
In one embodiment according to the present invention, the program memory may include a plurality of banks each of which stores one of the block programs so that the program is executed by the program executing unit sequentially executing the block program in each of the banks selected in a predetermined order.
Additionally, the data memory may include a plurality of banks each of which stores one of the data blocks so that the data block stored in one of the banks is used when each of the program block is executed by the program executing unit, the one of the banks being sequentially selected in a predetermined order.
According to the present invention, the program changing unit may store the new data in one of the banks of the program memory, the one of the banks having stored one of the block programs of which execution is completed. Accordingly, the block programs stored in each bank is replaced with a new program block after a block program stored in the one of the banks is completed. Thus, a plurality of algorithms can be performed by executing the block program in one of the banks sequentially selected in a predetermined order.
Additionally, the data processing unit may further comprise a block program obtaining unit obtaining the new block program from a first external memory each time an execution of the block program by the program executing unit is completed so as to provide the obtained block program to the program changing unit.
Additionally, the block program obtaining unit may store first load table information representing a relationship between phases of a program processing and the block program obtained from the first external memory. Thereby, the block program obtaining unit obtaining the new block program from the first external memory based on the first load table information.
Further, the data processing unit may further comprise a data changing unit obtaining a new data block from an external device each time execution of one of the block programs by the program executing unit is completed so as to store the obtained new data block in the data memory.
Additionally, the data processing unit may further comprise a data block obtaining unit obtaining the new data block program from a second external memory each time an execution of the block program by the program executing unit is completed so as to provide the obtained new data block to the data changing unit.
Additionally, the data block obtaining unit may store store table

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