Code translation between hardware design languages

Details Code translation between hardware design languages Code translation between hardware design languages

1998-11-12

2003-07-29

Jones, Hugh (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C716S030000

Reexamination Certificate

active

06601024

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to hardware design languages. More particularly, the present invention relates to an improved method for translating between Verilog and VHDL hardware design languages.
2. The Background
One well-known method for designing an ASIC or an FPGA-based digital circuit includes using an HDL (Hardware Description language). An HDL is a notation for describing an electronic circuit at a specified level of abstraction. Three types of abstraction levels are defined for an HDL: RTL (register-transfer level), gate-level, and transistor level. RTL abstraction describes the functional or behavioral characteristics of a circuit. Gate level abstraction describes a circuit using gate logic elements, such as OR, NOR, AND, NAND, and the like, and their interconnections, which form a netlist reflecting the circuit design when coupled together. The transistor level, sometimes referred to as a switch level, describes the circuit design usage transistors and their interconnections as the basic elements defining the properties of the circuit.
Specifying the level of abstraction enables a designer to model a circuit design at an abstraction level suitable for a particular design step. For example, if a top-down design process is used to implement a design specification, the designer may define a circuit design starting at a behavioral or functional level. This enables the designer to isolate the functional aspects of the proposed circuit design from testing and implementation (gate-level and/or target technology) issues that otherwise would have been complicating factors.
To minimize confusion in the following discussion, an HDL-based circuit design modeled at one of the above levels of abstraction will be referred to according to the level of abstraction used. For example, an HDL-based circuit design at the register-transfer level will simply be referred to as an RTL-based circuit design. Similarly, a structural circuit design at the gate level or at the transistor level will be referred to as a gate level-based circuit design or a transistor level-based circuit design, respectively.
Two types of hardware description languages are currently in wide use in the digital circuit design or EDA (Electronic Design Automation) industry: VHDL and Verilog HDL (hereinafter referred to as Verilog). VHDL is an abbreviation for VHSIC (very high-speed integrated circuit) Hardware Description Language. Both hardware description languages, however, are not compatible or interchangeable with respect to their respective tools, such as verification and simulation tools. This incompatibility, among other things, has promoted a divergence among design companies and companies that provide re-useable IP (Intellectual Property) core design modules into VHDL, and Verilog “camps.”
For example, a design company that is experienced in Verilog will typically look to Verilog-based re-useable modules as a source for design components, while a design company experienced in VHDL will typically look to VHDL-based re-useable modules. For a design company to switch to an HDL other than the one it is experienced with or to mix and match between the two types of HDLs would be too costly and/or inefficient. Re-useable Soft Intellectual Property (IP) Core vendors are also affected by the incompatibility between the HDLs because if they do not offer modules based on both types of HDLs, they risk losing market share to competitors that do.
One conventional solution to the above problems includes creating in a top-down manner an HDL-based circuit design at the register-transfer level (the “initial RTL-based circuit design”) and then translating the initial RTL-based circuit design to a target RTL-based circuit design. This approach includes at least three steps.
First, as shown in
FIG. 1
, a test bench
10
is created for the initial RTL-based design
12
so that a set of reference output vectors
18
may be obtained. Test bench
10
includes: a top-level module
14
representing a set of modules which comprise initial RTL-based design
12
, and a set of input test vectors
16
. Top-level module
14
is simulated using input test vectors
16
, generating a set of reference output vectors
18
, sometimes referred to as golden output vectors.
Second, as shown in
FIG. 2
, initial RTL-based circuit design
12
is translated into a target RTL-based circuit design
20
having a top-level module
38
using a code translation tool
21
. For example, if initial RTL-based circuit design
12
is described using VHDL, then the target RTL-based circuit design
20
is described using Verilog, or vice versa. The translation from one HDL type to another HDL type is performed on a module by module basis at the register-transfer level by a code translator. For example, the module tar
1
.mod
22
is created by translating the module org
1
.mod
24
from its initial RTL-based circuit design to the target RTL-based circuit design. Similarly, modules tar
2
.mod
26
, tar
3
.mod
28
, and tar
4
.mod
30
are created by translating the modules org
2
.mod
32
, org
3
.mod
34
, and org
4
.mod
36
, respectively, from their initial RTL-based circuit design to target RTL-based circuit design. After translation, target RTL-based circuit design
20
is typically checked for any coding violations.
Finally, as shown in
FIG. 3
, the translated files tar
1
.mod
22
, tar
2
.mod
26
, tar
3
.mod
28
, and tar
4
.mod
30
are integrated into a top-level module
38
after all of the initial modules have been translated. A top-level module includes a set of modules (typically all of the modules) which form a particular circuit design and describe the logical flow or arrangement of the modules with respect to each other. Hence, a top-level module is a fully hierarchical description of a set of modules that form a particular circuit design.
After integration, top-level module
38
is simulated by running a test bench
40
using test input vectors
16
, creating a set of test output vectors
42
. Test output vectors
42
are then compared with reference output vectors
18
to determine the accuracy of the translation.
The above approach suffers from the following disadvantages. First, all of the initial modules must be translated before the target modules can be integrated and tested. This prolongs the translation process because the integration of the target modules into a top-level module for simulation and testing cannot begin until the last initial module has been translated. For example, if org
1
.mod, org
2
.mod, org
3
.mod, and org
4
.mod require 1 day, 3 days, 5 days, and 15 days, respectively, to translate into their corresponding target modules, then integration and testing cannot begin until the end of the 15th day.
Moreover, testing is performed on the RTL-based top-level module, i.e., all of the target modules are tested at once. This renders debugging difficult (and hence increases verification time) because any problems encountered cannot be easily limited to one target module. This scenario is more complex especially when the logic path traverses multiple levels of hierarchy.
Accordingly, a need exists for an improved method for translating an initial RTL-based circuit design to a target RTL-based circuit design, which has a reduced translation and integration period.
Further, a need exists for an improved method for translating from an initial RTL-based circuit design to a target RTL-based circuit design, which ensures exact functional equivalence between the initial RTL-based and target RTL-based circuit designs.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, an HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules

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