Code tracking loop with automatic power normalization

Details Code tracking loop with automatic power normalization Code tracking loop with automatic power normalization

2001-12-27

2002-09-24

Vo, Don N. (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S149000, C375S150000

Reexamination Certificate

active

06456648

ABSTRACT:

BACKGROUND
The present invention relates to a code tracking system for a receiver of a code division multiple access (CDMA) communication system. More specifically, the present invention relates to a second order code tracking system for more effectively removing the timing difference between the transmitted code and the received code.
Synchronization is an important task in any kind of telecommunication. There are several levels of synchronization, such as, carrier, frequency, code, symbol, frame and network synchronization. In all these levels, synchronization can be distinguished into two phases, which are acquisition (initial synchronization) and tracking (fine synchronization).
A typical wireless communication system sends downlink communications from a base station to one or a plurality of User Equipments (UEs) and uplink communications from UEs to the base station. A receiver within the UE works by correlating, or despreading, the received downlink signal with a known code sequence. The sequence must be exactly synchronized to the received sequence in order to get the maximal output from the correlator.
The receiver should be able to easily adapt to a change in the environment of a radio line changing without ceasing operation. In order to accomplish this, present receivers gather as much of the transmitted signal energy as possible in order to maximize the signal-to-noise ratio. In multi-path fading channels, however, the signal energy is dispersed over a certain amount of time due to distinct echo paths and scattering. One crucial task of the receiver is thus to estimate the channel to improve its performance. If the receiver has information about the channel profile, one way of gathering signal energy is then to assign several correlator branches to different echo paths and combine their outputs constructively, a structure known as the RAKE receiver.
The RAKE receiver has several fingers, one for each echo path, and in each finger, the path delay with respect to some reference delay such as a direct or the earliest received path, must be estimated and tracked throughout the transmission. The estimation of the paths initial position in time is obtained by using a multi-path search algorithm. The multi-path search algorithm does an extensive search through correlators to locate the paths with a chip accuracy. After these initial positions are found, the tracking units generate accurate estimates for the delays of several multi-path components by means of early-late timing error detectors and utilize these estimates for the different delays to shift the phase of the codes. This type of tracking unit is known as an early-late gate synchronizer. A delay-locked loop (DLL) is commonly used to implement the early-late gate synchronizer. Illustrated in
FIG. 1
is a block diagram of this delay-locked loop. The bandwidth of the Code Tracking Loop (CTL) determines the noise filtering capability of the synchronizer. The narrower the bandwidth, the more robust the synchronizer is to distortion from noise and less sensitive to small signal changes. The bandwidth of the loop depends on the parameters of the loop filter (alpha, beta), total loop gain (K
T
), and input signal power level (P
in
). Damping ratio of the loop also depends on the same parameters. Damping ratio of the loop determines the stability of the loop. Although the parameters of the loop can be fixed, it is very difficult to fix the input signal level.
Most of the digital receivers employ some form of Automatic Gain Control (AGC) in their physical layers. Although AGC limits the input signal level, the dynamic level of the signal level is still large. This is due to the fact that AGC is actually designed to prevent the Analog to Digital Converter (ADC) from entering saturation.
Since the dynamic range of the input signal level is not effectively limited, the bandwidth and damping ratio of the code tracking loop changes with input signal power. This results in degradation in performance for the code tracking loop.
Accordingly, there exists a need for a code tracking loop that maintains the bandwidth and damping ratio of the loop regardless of changes with the input signal power level.
Other objects and advantages of the present invention will become apparent after reading the description of the preferred embodiment.
SUMMARY
The present invention is a receiver, included in a user equipment (UE), of a code division multiple access (CDMA) communication system which includes the UE and a plurality of base stations. The UE is in communication with one of the plurality of base stations and receives a communication signal from the base station through the receiver. The communication signal is correlated by said receiver using a delay locked code tracking loop, that estimates and tracks a channel delay of the communication signal. The tracking loop comprises a reference code generator for generating a reference code signal and an interpolator for generating timed signal versions in response to the receipt of said communication. A timed signal correlator, also included in the track loop for correlating at least two of the timed signal versions with the code reference signal. The result of the correlation is used for generating an error signal. An automatic power normalization loop (APN), which is responsive to the interpolator, generates a power error signal that is used to normalize the error signal through a normalization circuit.


REFERENCES:
patent: 5737362 (1998-04-01), Hyun et al.
patent: 5768323 (1998-06-01), Kroeger et al.
patent: 5832023 (1998-11-01), Latva-aho
patent: 6201828 (2001-03-01), El-Tarhuni et al.
patent: 6205167 (2001-03-01), Kamgar et al.
Floyd M. Gardner, Interpolation in Digital Modems-Part I: Fundamentals, IEEE, Transactions on Communications, vol. 41, No. 3, pp. 501-507, Mar. 1993.
Gardner et al., Interpolation in Digital Modems-Part II: Implementation and Performance, IEEE Transactions on Communications, vol. 41, No. 6, pp. 998-1008, Jun. 1993.
Lim et al., Analysis of Decimator-Based Full-Digital Delay-Locked PN Code Tracking Loops for Bandlimited Direct-Sequence Spread-Spectrum Signals in AWGN, IEICE Transactions on Communications, vol. E00-A, No. 1, Jan. 1998.
3GPP TSG RAN, UE Radio Transmission and Reception (FDD), 3G TS 25.101, V3.2.0, Mar. 2000.
Latva-aho et al., Quasi-Coherent Delay-Locked Loops for Fading Channels.
Jack K. Holmes, Coherent Spread Spectrum Systems, John Wiley and Sons Inc., pp. 475-481 and pp. 80-81, New York, 1982.
Su et al., Performance of Combined DDLL and AGC Loop Direct-Sequence Spread-Spectrum Systems, IEEE Transactions on Communications, vol. 48, No. 9, pp. 1455-1458, Sep. 2000.

Affiliated with

Also associated with

Rating

Code tracking loop with automatic power normalization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Code tracking loop with automatic power normalization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Code tracking loop with automatic power normalization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2855669