Code sequence for asynchronous backing store switch utilizing bo

Details Code sequence for asynchronous backing store switch utilizing bo Code sequence for asynchronous backing store switch utilizing bo

1998-04-21

2000-08-29

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

710264, 709108, G06F 930

Patent

active

061122920

ABSTRACT:
A computer implemented method for switching from an interrupted context to an interrupting context in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) that exchanges information, in one of instruction execution dependent and independent modes between the second portion and a storage area. The method includes the following steps: a state of the RSE of the interrupted context is preserved; a COVER instruction is issued; a first (BSPSTORE) pointer is preserved. The first pointer points to a location in the storage area, of the interrupted context, where a next register of the second portion is to be written; first pointer is written with a value corresponding to the interrupting context; and a second pointer (BSP) is preserved. The new first and second pointers in the interrupting context define the storage area of RS values associated with the interrupted context. The new first pointer is subtracted from the second new pointer. The difference (number of dirty registers) is deposited into the RSC.loadrs field. A LOADRS instruction is issued to load the RS with all interrupted context values. The original first BSPSTORE is restored from the preserved BSPSTORE.

REFERENCES:
patent: 5161226 (1992-11-01), Wainer
patent: 5327566 (1994-07-01), Forsyth
patent: 5428779 (1995-06-01), Allegrucci et al.
patent: 5535397 (1996-07-01), Durante et al.
patent: 5564031 (1996-10-01), Amerson et al.
patent: 5640582 (1997-06-01), Hays
patent: 5717933 (1998-02-01), Mann
A VLSI RISC, David A. Patterson and Carlo H. Sequin, Computer Magazine, vol. 15, No. 9, (ISSN 0018-9162) Sep., 1982, pp. 8-21.
RISC Systems, Daniel Tabak, Microprocessors and Microsystems, vol. 12, No. 4, May, 1988, pp. 179-185.
A Simple Interprocedural Register Allocation Algorithm and Its Effectiveness for LISP, Peter A. Steenkiste and John L. Hennessy, acm Transactions on Programming Languages and Systems, vol. 11, No. 1, Jan., 1989, pp. 1-32.
Register Stack, AM29040 Microprocessor User Manual, 29K Family, Rev. A. May 1994, pp. 4-3 -4-16.
Software Considerations, David L. Weaver/Tom Germond, The SPARC Architecture Manual, Version 9, 1994, pp. 291-294.

Affiliated with

Also associated with

Rating

Code sequence for asynchronous backing store switch utilizing bo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Code sequence for asynchronous backing store switch utilizing bo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Code sequence for asynchronous backing store switch utilizing bo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1259751