Code sensing method and apparatus

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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C714S796000

Reexamination Certificate

active

07359463

ABSTRACT:
The present invention establishes a metric calculation method. A constant calculation circuit31calculates constants V/2−A, V/2+A, and A/2, which are required to calculate branch metrics by using an average voltage V/2, corresponding to a parameter R input from an asymmetrical register, which is input from an average voltage register, and output them to adders33, 35, and36, respectively. A multiplier32multiplies an equalized signal ykby a value P of 1 or −1 input from a polarity register. A bit shifter37shifts by c bits A/2−yk, corresponding to the parameter R input from the asymmetrical register, which is input from the adder36. That is, the bit shifter37multiplies A/2−ykby α, and outputs it to adders38and39. However, when the parameter R is 0, the bit shifter37outputs 0 to the adders38and39. The present invention can be applied to a recording and reproduction apparatus.

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patent: 6718511 (2004-04-01), Kravtchenko et al.
patent: 2002/0114411 (2002-08-01), Nakano et al.
patent: 0 644 661 (1995-03-01), None
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patent: 8-221904 (1996-08-01), None
Webster's II New Riverside University Dictionary, Hougton Mifflin Company, 1988, p. 307.
L. Fredrickson, “Trellis Coding in the Venus FRML Read/Write Channel,” IEEE Transactions on Magnetics, vol. 33, No. 5, Sep. 1997.

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