Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2005-07-04
2009-08-11
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S17700V, C331SDIG002, C708S271000, C327S107000, C342S357490
Reexamination Certificate
active
07573337
ABSTRACT:
A code is provided which outputs a predetermined code enable signal by executing a simple control, depending on a clock signal frequency, with an optimal circuit scale. A multiplexer receives integers which are relatively prime, and outputs either of them to an adder, depending on comparator output signal. The adder adds an integer latched by the register and an integer output by the multiplexer, and outputs the result via a multiplexer to the register. The register latches and outputs the received integer to the comparator with a sampling clock signal frequency. In accordance with a threshold set based on the integers and the number of bits of the adder or the register, the comparator outputs a signal having the High state only when the output integer of the register satisfies the threshold condition. The code outputs this as a code enable signal.
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Thompson, “Low-Latency, High-Speed Numerically Controlled Oscillator Using Progression-of-States Technique,” IEEE Journal of Solid-State Circuits, 27:113-117 (1992).
Okada Tsutomu
Wang Dun
Edwards Angell Palmer & & Dodge LLP
Furuno Electric Company Ltd.
Johnson Ryan J.
Pascal Robert
Toppin Catherine J.
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