Code independent charge transfer scheme for...

Details Code independent charge transfer scheme for... Code independent charge transfer scheme for...

2001-02-16

2002-08-20

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S144000, C341S172000

Reexamination Certificate

active

06437720

ABSTRACT:

FIELD OF THE INVENTION
The disclosure relates to switched-capacitor digital-to-analog (DAC) converter circuitry in which crossing switches for each capacitor are used thereby eliminating any cross interference between blocks sharing the same reference voltages.
BACKGROUND OF THE INVENTION
Switched-capacitor digital-to-analog (DAC) converters are popular blocks in mixed-signal chips. Differential structures are typically used in switched-capacitor DAC to suppress noise and odd order harmonic distortion.
Referring now to
FIG. 1
, as is conventional for a switched-capacitor circuit, control signals &PHgr;
1
and &PHgr;
2
(timing signals) operate in two non-overlapping time intervals (or clock phases).
With each input capacitor's equal size (a m bit DAC has 2
m
−1=n unit element capacitors) or multiple of unit size capacitor for better matching, a typical implementation of a fully differential switched-capacitor DAC is depicted in
FIG. 2
, in which a prior art switched-capacitor DAC system is shown including a DAC
10
and an integrator
20
. During clock phase &PHgr;
1
, DAC
10
samples a reference voltage and during clock phase &PHgr;
2
transfers charge to integrator
20
together with negative reference v
ref
n
12
(−v
ref
) and positive reference v
ref
p
11
(+v
ref
). Reference voltages v
ref
p
11
and v
ref
n
12
may be considered as input voltages to DAC
10
. Integrator
20
includes an operational amplifier (op amp)
21
, a first integrator capacitor
22
connected between non-inverting output lead
23
and inverting input lead
24
, and a second integrator capacitor
25
connected between inverting output lead
26
and non-inverting input lead
27
.
Switched-capacitor DAC
10
includes input lines
11
and
12
receiving the positive and negative terminals of a reference voltage v
ref
. A first set of input capacitors
13
are coupled to input lines
11
and
12
through a first switching circuit
14
and to the input leads
24
and
27
of op amp
21
through a second switching circuit
15
. A second set of input capacitors
16
as part of a fully differential structure are similarly coupled to input lines
11
and
12
through first switching circuit
14
and to input leads
24
and
27
of op amp
21
through second switching circuit
15
. Capacitors
13
and
16
sample (i.e., are charged by) the reference voltage v
ref
through switching circuit
14
and transfer charge to capacitors
22
and
25
through switching circuit
15
. The values of capacitors
13
and
16
are preferably equal as are the values of capacitors
22
and
25
.
Depending on the individual digital code signal y
i
and y
ib
where y
ib
is the complement of y
i
, i=1, 2, . . . n. If all y
i
equal to 1 represents maximum value of DAC and all y
i
equal to 0 represents minimum value of DAC. To an m bit DAC, y
i
and y
ib
can be derived from a binary (or 2's complementary) code to thermometer code converter. Switching circuit
14
includes switches
17
which are controlled by combination logic &PHgr;
1
y
i
+&PHgr;
2
y
ib
of (timing signal) &PHgr;
1
, &PHgr;
2
and digital code y
i
and y
ib
, where i=1,2, . . . , n and the switches
18
which are controlled by a different way of &PHgr;
1
y
i
+&PHgr;
2
y
ib
of &PHgr;
1
, &PHgr;
2
and digital code y
i
and y
ib
, where i=1,2, . . . , n. Switching circuit
15
includes switches
19
and
30
, switches
19
being controlled by signal &PHgr;
1
alone and switches
30
being controlled by signals &PHgr;
2
alone see FIG.
1
.
Switching circuit
14
includes a first set of switches
17
connected between input lines
11
and the left plate of capacitors
13
. A second switch
18
is connected between input lines
12
and the left plate of capacitor
13
. A set of switches
17
are connected between input lines
12
and the left plate of capacitors
16
. A set of switches
18
are connected between input line
11
and the left plate of capacitors
16
. Switching circuit
15
includes a first switch
19
connected between the right plate of capacitors
13
and the inverting input lead
24
of op amp
21
and similarly a second switch
19
connected between the right plate of capacitors
16
and the non-inverting input lead
27
of op amp
21
. A switch
30
is connected between the right plate of capacitors
13
and the non-inverting input lead
24
of op amp
21
. Similarly, a switch
30
is connected between the right plate of capacitor
16
and the non-inverting input lead
27
of op amp
21
. Switches
19
are controlled by a control signal &PHgr;
1
while switches
30
are controlled by a control signal &PHgr;
2
.
As should be readily understood by those skilled in the art, input capacitors
13
and
16
operate to sample reference voltages
11
and
12
through switching circuit
14
and transfer charge to integrating capacitors
22
and
25
through switching circuit
15
. The arrangement of input capacitors enables reference voltages to be sampled during both time intervals and charge to be transferred during both time intervals. The timing diagram of
FIG. 1
assumes that the digital code signal y
i
remains stable during a single period of signals &PHgr;
1
and &PHgr;
2
. The DAC of
FIG. 2
operates effectively to draw charge from references v
ref
p
and v
ref
n
and the charge depends on the previous digital code. Since references v
ref
p
and v
ref
n
always have certain output impedance, the derivative of the output signals
32
and
33
will ride on the references, thereby creating cross coupling and interference with other circuit blocks sharing the same references.
Accordingly, there is a need for a code-independent charge transfer scheme for switched-capacitor digital-to-analog converters which reduces complexity of the voltage references and achieves signal-independent charge drawn from the reference, without the use of multiple references or dummy circuitry or without using references with very low output impedance.
SUMMARY OF THE INVENTION
An exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal. The DAC system includes a first switched-capacitor branch
80
and a second switched-capacitor branch which are dependent on the digital code signals. Further, the DAC system includes another switching circuit that includes a first and second sampling switch and a first and second discharge switch. The first and second sampling switches operate substantially in unison to sample signals from the first branch circuit and the second branch circuit and provide an output to an integrator.
Another exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal. The DAC system includes at least one digital code dependent switching circuit, receiving the digital code signal. The DAC system also includes at least one reference input switching circuit. Then the at least one reference input switching circuit isolates from the digital code dependent switching circuit by at least one capacitor.
Yet another exemplary embodiment of the present invention relates to a switched-capacitor DAC system configured to receive a digital code signal having an integrator circuit including an op amp having first and second input leads, first and second output leads, and first and second integrator capacitors respectively connected between the first and second input leads and the first and second output leads. The DAC system includes a first switching circuit coupled to a reference input. The first switching circuit output is dependent on the digital code signal. The DAC system also includes at least one first input capacitor to be charged through the reference inputs and the first switching circuit. Further, the DAC system includes a second switching circuit coupled to the reference input. The first switching circuit output is dependent on the digital code signal. Further still, the DAC system includes at least one second input capacitor to be

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