Code generation device, semiconductor device, and receiver...

Details Code generation device, semiconductor device, and receiver... Code generation device, semiconductor device, and receiver...

2003-01-15

2004-06-22

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Reexamination Certificate

active

06753795

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2002-029170, filed on Feb. 6, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a code generation device, a semiconductor device, and a receiver device. In particular, the present invention relates to a code generation device which generates a predetermined code, a semiconductor device including a code generation device which generates a predetermined code, and a receiver device which generates a predetermined code, and decodes a received signal by using the predetermined code.
2) Description of the Related Art
In the spread spectrum communication methods, spreading modulation is performed for transmission by using a different spreading code for each communication channel. On the receiver side, reverse spreading must be performed by using the same spreading code as that used on the transmitter side. Therefore, it is necessary to detect the spreading code and establish a timing of the spreading code in initial synchronization.
As a method of initial synchronization, the three-stage initial synchronization method is known. In the three-stage initial synchronization method, chip synchronization is established in the first stage, a spreading code group is identified and a frame timing is established in the second stage, and a spreading code is identified in the third stage.
In the second and third stages, a challenge which is to be solved for improving system performance is to identify one of a plurality of types of spreading codes at the earliest possible time. In the case where a matched filter is used, a received baseband signal is stored, a correlation between the received baseband signal and a sequence of a plurality of spreading codes is detected, and detection of a spreading code and establishment of the timing of the spreading code are achieved.
A construction of a circuit of a conventional initial synchronization device using a matched filter is explained with reference to FIG.
8
. The initial synchronization device in
FIG. 8
comprises a code generation circuit
10
, a serial-to-parallel conversion circuit
11
, a shift register
12
, multipliers
13
-
1
to
13
-m, and an adder
14
. The initial synchronization device generates a hierarchized orthogonal code, and calculates and outputs a correlation value between the hierarchized orthogonal code and a received baseband signal.
The code generation circuit
10
comprises a channelization-code number generation circuit
10
a
, a scrambling-code number generation circuit
10
b
, a channelization-code generation circuit
10
c
, a scrambling-code generation circuit
10
d
, and a multiplier
10
e
. The code generation circuit
10
generates and outputs a spreading code.
The channelization-code number generation circuit
10
a
is a number fixedly assigned to each user.
The scrambling-code number generation circuit
10
b
is a number for designating a Gold code as a scrambling code.
The channelization-code generation circuit
10
c
generates a hierarchized orthogonal code corresponding to the channelization-code number generation circuit
10
a.
The scrambling-code generation circuit
10
d
generates a Gold code corresponding to the scrambling-code number
10
b.
The multiplier
10
e
calculates and outputs bitwise exclusive logical sums between the hierarchized orthogonal code output from the channelization-code generation circuit
10
c
and the Gold code output from the scrambling-code generation circuit
10
d.
The serial-to-parallel conversion circuit
11
converts a (serial) bit signal output from the multiplier
10
e
, into a parallel signal, and outputs the parallel signal.
The shift register
12
receives a baseband signal, shifts the received baseband signal bit by bit, and outputs the shifted result as a parallel signal to the multipliers
13
-
1
to
13
-m.
The multipliers
13
-
1
to
13
-m calculate and output bitwise products of the parallel signal output from the serial-to-parallel conversion circuit
11
and the parallel signal output from the shift register
12
.
The adder
14
calculates a sum of the outputs of the multipliers
13
-
1
to
13
-m, and outputs the sum as a “correlation output.”
Next, details of the construction of the channelization-code generation circuit
10
c
illustrated in
FIG. 8
are explained with reference to FIG.
9
. As illustrated in
FIG. 9
, the channelization-code generation circuit
10
c
comprises a code-phase generation circuit
20
, AND gates
21
to
29
, an EXCLUSIVE-OR gate
30
, and a register
31
.
The code-phase generation circuit
20
generates and outputs data 0 to 511 as a code phase.
The AND gates
21
to
29
calculate and output bitwise logical products of the hierarchical-orthogonal-code number k as the channelization-code number
10
a
and the code phase n output from the code-phase generation circuit
20
.
The EXCLUSIVE-OR gate
30
calculates and outputs an exclusive logical sum of the outputs of the AND gates
21
to
29
.
The register
31
stores and outputs all bits of data (as hierarchized orthogonal codes C
k,n
) output from the EXCLUSIVE-OR gate
30
.
Next, the operations of the above conventional example are explained. As an example, the operations for timing synchronization are explained below.
The channelization-code generation circuit
10
c
receives a channelization-code number
10
a
which is assigned to each user, and generates a channelization code corresponding to the channelization-code number
10
a.
Thus, a plurality of bits constituting the hierarchical-orthogonal-code number k as the channelization-code number are respectively supplied to the AND gates
21
to
29
in the channelization-code generation circuit
10
c
. On the other hand, the code-phase generation circuit
20
successively generates the data 0 to 511 as the code phase, and a plurality of bits constituting the data of the code phase are respectively supplied to the AND gates
21
to
29
. At this time, the plurality of bits of the code phase data supplied to the AND gates
21
to
29
are arranged in reverse order to the plurality of bits of the hierarchical-orthogonal-code number k supplied to the AND gates
21
to
29
.
The AND gates
21
to
29
calculate and output bitwise logical products of the hierarchical-orthogonal-code number k as the channelization-code number generation circuit
10
a
and the code phase n output from the code-phase generation circuit
20
.
The EXCLUSIVE-OR gate
30
calculates and outputs an exclusive logical sum of the outputs of the AND gates
21
to
29
.
The register
31
stores bit data being output from the EXCLUSIVE-OR gate
30
and corresponding to the code phase 0 to 511, and outputs the bit data as hierarchized orthogonal codes.
On the other hand, the scrambling-code generation circuit
10
d
generates and outputs a Gold code as a scrambling code corresponding to the scrambling-code number generation circuit
10
b
. The Gold code is basically a code sequence obtained by adding two M-sequences having an identical period, and has a code length corresponding to a plurality of symbol lengths while the code length of the channelization code is the symbol length.
The multiplier
10
e
calculates and outputs a product of the data output from the channelization-code generation circuit
10
c
and the data output from the scrambling-code generation circuit
10
d
. As mentioned before, the bit length of the scrambling code is greater than the bit length of the channelization code. Therefore, the channelization-code generation circuit
10
c
repeatedly outputs identical codes, and the multiplier
10
e
calculates and outputs bitwise exclusive logical sums, a product of the scrambling code and the channelization code which is repeatedly output.
The serial-to-parallel conversion circuit
11
stores the serial data output from the multiplier
10
e
, in a register built in the serial-to-parallel c

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