Code division multiplex communications system

Multiplex communications – Communication over free space – Combining or distributing information via code word channels...

Reexamination Certificate

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Details

C370S479000, C375S143000, C375S152000

Reexamination Certificate

active

06201800

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to spread spectrum communications and more particularly to a low power consumption code division multiplex communications system.
While other multiplex communication systems (FDMA, TDMA) cannot permit more than a predetermined number of users, in a code division multiple access (CDMA), since the quality of communication gradually deteriorates (graceful degradation), users can be accepted as long as the code synchronization can be set so that increase in the number of users can be expected. The CDMA has excellent interference resistance, signal concealment, and fading resistance and is being used in a wide range.
According to the CDMA communications system, in a transmitter, baseband data to be transmitted is multiplied by a spread code and further by a carrier, and resultant data is transmitted from an antenna. In a receiver, a spread code having the same phase as that of the spread code at the time of transmission is prepared and the baseband data is decoded by using a correlator.
Hitherto, sliding correlator, SAW (Surface Acoustic Wave) matched filter, digital LSI matched filter, and the like are known as correlators.
According to the sliding correlator, the spread code is cycled faster than a reception signal and a pull-in is performed by a discriminating circuit having a DLL (Delay Locked Loop) or the like. A signal obtained by eliminating carrier components by a sync detector or equivalent means, that is, of a frequency which is about the chip rate is inputted to the sliding correlator. The sliding correlator needs chip synchronization and has drawbacks that it takes time to capture synchronization and that the reception signal including carrier components cannot be inputted to the sliding correlator.
In the SAW matched filter, chip synchronization can be obtained at high speed. Although it can be used in the RF and IF bands, there are drawbacks that since the spread code is decided by a physical pattern of an SAW device, it is difficult to change the code and the filter does not easily correspond to a long spread code.
In the digital LSI matched filter, the chip synchronization is unnecessary. Although there is an advantage that the spread code can be easily changed, there is a drawback of a large power consumption. In the digital LSI matched filter according to conventional CMOS integrated circuit techniques, since the operating speed is slow, there is a drawback that it can be generally used only in the baseband.
In recent years, a mobile communication (portable telephone and the like) is being widely spread. As a communication system employed by the mobile communication, attention has been paid most to the above-mentioned CDMA. The correlator of the CDMA used in the mobile communication is requested to have programmability of the spread code and small power consumption.
However, the SAW matched filter has a problem regarding the programmability of the spread code. On the other hand, the digital LSI matched filter has a drawback of a large power consumption.
Recently, a correlator using a switched capacitor system has been developed and is being put into practical use. The correlator is accomplished by further improving the digital LSI matched filter and has power consumption of about {fraction (1/10)} of that of the digital LSI matched filter.
SUMMARY OF THE INVENTION
The invention has been made in consideration of the background and it is an object of the invention to provide a code division multiplex communications system having programmability of the spread code and the power consumption which is markedly smaller than that of the conventional technique.
According to the invention, there is provided a code division multiplex communications system comprising: receiving means for receiving a radio wave and transforming the radio wave to an electric signal; delaying means for sequentially reading the electric signal at a timing of a clock pulse; switching means for shutting off a drive current of the delaying means at an OFF timing of the clock pulse; adding and subtracting means for adding and subtracting outputs of the delaying means in accordance with a spread code; and reproducing means for reproducing a transmission signal on the basis of an output of the adding and subtracting means.
Preferably, in the code division multiplex communications system, the receiving means receives the radio wave and transforming the received signal to an intermediate frequency signal.
Preferably, in the code division multiplex communications system, the receiving means receives the radio wave and transforms the received radio wave to a baseband signal.
Preferably, in the code division multiplex communications system, the delaying means has voltage-current converting means and current delaying means, converts the electric signal to a current signal, and after that, sequentially reads the current signal by the current delaying means at the timing of the clock pulse.
Preferably, in the code division multiplex communications system, the current delaying means is constructed by current flip-flops of the number twice as many as the number of chips of the spread code.
Preferably, in the code division multiplex communications system, the current flip-flop is constructed by serially connecting a first sample and hold circuit for sampling an input current at the leading edge of a first clock pulse and holding at the trailing edge of the first clock pulse and a second sample and hold circuit for sampling an input current at the leading edge of a second clock pulse and holding at the trailing edge of the second clock pulse.
Preferably, in the code division multiplex communications system, the adding and subtracting means comprises: spread code output means for outputting a spread code; switching means for connecting each output of the current delaying means to a first or second current path to perform current addition on the basis of the output of the spread code output means; and subtracting means for subtracting the current of the second current path from the current of the first current path.
Preferably, in the code division multiplex communications system, the adding and subtracting means comprises: spread code output means for outputting the spread code; adding means for connecting outputs of the current delaying means to the first or second current path on the basis of an output of the spread code output means and adding currents; subtracting means for subtracting a current of the second current path from a current of the first current path; and switching means for turning off the operation of the adding means and subtracting means at an OFF timing of the clock pulse.
Preferably, in the code division multiplex communications system, in the subtracting means, first and second current mirror circuits are connected in series, a current of the second current path is supplied to an input terminal of the first current mirror circuit, a current of the first current path is supplied to an output terminal of the first current mirror circuit and an input terminal of the second current mirror circuit, and an output is obtained from an output terminal of the second current mirror circuit.
Preferably, in the code division multiplex communications system, the reproduction means comprises: a current-voltage converter for converting an output of the adding and subtracting means to a voltage signal; and a demodulator for reproducing the transmission signal by integrating an output of the current-voltage converter.


REFERENCES:
patent: 3643230 (1972-02-01), Lynes
patent: 4164628 (1979-08-01), Ward et al.
patent: 4653069 (1987-03-01), Roeder
patent: 5276704 (1994-01-01), Dixon
patent: 5331230 (1994-07-01), Ichihara
patent: 5416737 (1995-05-01), Lingstaedt et al.
patent: 5809064 (1998-09-01), Fenton et al.
patent: 43 17 188 A1 (1995-02-01), None
patent: 0 535 808 A2 (1993-04-01), None
“Low Power Consumption Matched Filter LSI for Wideband”,Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE., Mamoru Sawahashi,

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