Code conversion arrangements for addresses to faulty memory loca

Details Code conversion arrangements for addresses to faulty memory loca Code conversion arrangements for addresses to faulty memory loca

1975-04-16

1976-11-16

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

3401725, G11C 800, G11C 2900

Patent

active

039927024

ABSTRACT:
A code converter comprising a pair of memories which are addressed by respective halves of the input code. The outputs of the memories are concatenated to provide an address for a third memory. The output of the third memory provides the output code. The converter is initially set by applying the desired input codes in sequence, and writing the contents of a counter into the addressed locations of the three memories, the counter being incremented for each new input code. A particular example of the use of such a converter is for assigning replacement addresses in an auxiliary memory for faulty locations in a main memory.

REFERENCES:
patent: 3573751 (1971-04-01), De Lisle
patent: 3659275 (1972-04-01), Marshall
Abrahamsen, Dynamic Redundancy and Repair System for Large Mass Storage Unit, IBM Technical Disclosure Bulletin, vol. 17, No. 10, 3/75, pp. 2841-2843.

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