Code addressable memory cell in flash memory device

Details Code addressable memory cell in flash memory device Code addressable memory cell in flash memory device

2000-12-27

2002-07-23

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S185260, C365S149000, C365S185010

Reexamination Certificate

active

06424568

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a flash memory device; and more particularly, to a code addressable memory (CAM) cell in a flash memory device.
DESCRIPTION OF THE PRIOR ART
A flash memory device is a nonvolatile memory device capable of electrically erasing and programming. The flash memory device performs protection
onprotection of code information that needs to be protected during a use of a flash memory product and performs repair required to increase a yield in a progress of performing a product test.
FIG. 1A
shows roughly a section of a conventional code addressable memory (CAM) cell of a flash memory device.
FIG. 1B
is a circuit diagram equivalent to the conventional CAM cell shown in FIG.
1
A.
As shown in
FIG. 1A
, a floating gate
12
and a control gate
13
are stacked on a semiconductor substrate
11
to thereby form a gate. Also, a source (S) and a drain (D) are formed on the semiconductor substrate
11
. The conventional CAM cell has the same architecture as a main cell as shown in the drawing.
Generally, to read out information of a cell, it is required that a predetermined voltage is applied to the control gate and current quantity flowing into the drain is sensed. Mostly a power source voltage (V
cc
) is directly used as the voltage applied to the control gate in order to reduce a time delay that it will take to perform the read operation in utilizing a boosting voltage internally in the flash memory device. However, in this case, there is caused a problem that the current quantity flowing into the drain is too small to sense.
That is to say, at a read operation of the CAM cell, a conductance of the cell (G
m
) is dropped by a coupling ratio about 0.55 that is generated at a dielectric layer between the floating gate
12
and the control gate
13
. Also, in a threshold voltage (V
T
) of 2.0 V, as an operation voltage gets lower, which operates the memory device and is used as a control gate voltage, the cell current quantity is suddenly decreased. Accordingly, it is difficult to read out cell information and thus, it is unavoidable to get a cell threshold voltage lower than 0V in order to perform data sensing by erasing the cell excessively.
However, erasing the cell excessively caused a problem that data is not easy to keep in store for long time, due to a leakage current of the cell under lots of disadvantageous environments where high temperature, high voltage or the like are generated.
Also, the flash memory device needs to be capable of keeping data in store for about 10 years and it is required to form a tunnel oxide layer and an inter-layer insulating layer thickly in order to satisfy the capability. At this point, it is not easy to perform a vertical shrink of the cell in a high-integrated device. Accordingly, since a limitation of data storage capability of the cell keeps the tunnel oxide layer and the inter-layer insulating layer from being formed thin, the cell current quantity can't be increased to thereby be difficult to read out Information of the main cell.
Therefore, it is general to read out the cell information by raising the cell gate voltage using a word line boosting circuit.
However, adding the boosting circuit in the flash memory device causes space for a neighboring circuit to become wider and also, there is a problem that a performance of the device is dropped since it takes an undesired latency time to read out the data stored in the CAM cell.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a code addressable memory (CAM) cell included in a flash memory device that can be operated stably at a low voltage by increasing a coupling rate of the CAM cell
In accordance with an aspect of the present invention, there is provided a code addressable memory (CAM) included in a flash memory device comprising a unit cell including a floating gate and a control gate; and a gate coupling unit coupled to the unit cell or further comprising a switching circuit for connecting and disconnecting the unit cell with the gate coupling unit respectively at a read operation of the CAM and a programming or an erasing operation of the CAM.


REFERENCES:
patent: 5243575 (1993-09-01), Sambandan et al.
patent: 5485595 (1996-01-01), Assar et al.
patent: 5917743 (1999-06-01), Roy
patent: 6002614 (1999-12-01), Banks
patent: 6005790 (1999-12-01), Chan et al.
patent: 6044017 (2000-03-01), Lee et al.
patent: 6125055 (2000-09-01), Kasa et al.
patent: 407030002 (1995-01-01), None
patent: 02000150683 (2000-05-01), None

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