Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-12-03
2002-11-26
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S714000, C438S715000, C438S719000, C438S721000
Reexamination Certificate
active
06486069
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to silicide etch processes and apparatus generally and, in particular, to cobalt silicide etch processes and apparatus.
BACKGROUND OF THE INVENTION
Since the sheet resistance of metal suicides is much lower than polysilicon, metal silicides are commonly used as a cladding on polysilicon to reduce power consumption and the RC time constant in microelectronic integrated circuits. Of all known silicides, cobalt silicide has the lowest sheet resistance and is thus the most desirable silicide for microelectronic integrated circuit use. The introduction of silicides, and particularly of cobalt silicide, for microelectronic integrated circuit fabrication has, however, been limited by the severe difficulty of etching these materials. The reason for the etch difficulty of cobalt silicide is that cobalt has no known compounds that can serve as volatile etch reaction products at temperatures below 500° C. (Handbook of Chemistry and Physics).
SUMMARY OF THE INVENTION
Accordingly, the present invention has been developed to solve the problem of the etching of silicides and, in particular, cobalt silicide. The invention includes both a method and apparatus for accomplishing this task.
The method of processing a silicide layer which is included in a layer stack positioned on a substrate includes the steps, in any order, of performing a process which can hold the substrate at a first temperature and changing the temperature of the substrate in order to process the silicide layer at a second temperature.
A method and apparatus of the invention provides for processing a silicide layer which is included in the layer stack with another layer including the steps, in any order, of processing the silicide layer at an elevated temperature and processing another layer at a lower temperature.
More specifically, the process includes etching a layer stack including the silicide and at least one of an oxide and a polysilicon. The process includes performing the etching of the silicide at an elevated temperature and performing the etching of the other layers at lower temperatures. Such a process can occur in a single etch reactor or in two etch reactors, with the silicide etch step occurring in a different reaction than the polysilicon etch step. By such a mechanism, anisotropic etching of both the silicide and the other layers can be accomplished. Additionally such a method utilizes the rapid cooling and/or heating of the wafer in order to bring the wafer temperature to the appropriate, range for etching of the relevant layer.
In another preferred aspect of the invention, the silicide layer is etched at a temperature of 150° C. or above while the remaining layers of the layer stack are etched at approximately 80° C. or below.
In an aspect of the invention, the suicide layer can preferably include cobalt silicide. Other silicide layers can include tantalum silicide, titanium silicide, or molybdenum silicide. Further, the other layers can include, by way of example, an oxide layer and/or polysilicon layers.
The novel method is carried out in a novel apparatus which is designed for handling hard to process silicide films as well as for effectively handling the remaining film. Such an apparatus, preferably, has a high selectivity to oxide films. In particular, the unique apparatus includes a reactor having a tri-electrode configuration. In one embodiment, the method is carried out in such a tri-electrode reactor having first and second electrodes and a side peripheral electrode. The second electrode is provided with high and low frequency power supplies. The side peripheral electrode can alternatively be provided with a high frequency power supply. This reactor includes a chuck which can rapidly change and maintain the temperature of the wafer at advantageous levels in order to process silicide layers and, alternatively, to process other layers, including by way of example, oxide layers and polysilicon layers.
Alternatively, the silicide films can be processed in a tri-electrode reactor chamber wherein the chuck electrode is provided with low and high frequency power supplies. The side peripheral electrode can be grounded or floating. Alternatively, the side peripheral electrode can be supplied with a low frequency power supply. With such an arrangement it is again preferable that the chuck is configurated in order to be able to rapidly change the temperature of the wafer. Preferably for such an arrangement, other layers such as oxide and polysilicon layers can be processed in a separate reactor which is first described herein above with the high frequency power supply communicating with the side peripheral electrode.
It is to be understood that the above described reactors are generally considered capacitively coupled reactors and that other reactors including inductively coupled reactors can be used and be in accordance with the invention. Thus, still alternatively, the invention can be practical in an inductively coupled di-electrode or tri-electrode reactor. In one embodiment, the top inductive coil electrode would be at a high frequency and the bottom electrode associated with the chuck would be at a low frequency. Both steps of etching a silicide layer and a non-silicide layer could be performed in the same chamber. If such a inductively coupled reaction had multiple etch chambers, if desired, a silicide etch step could be performed in one chamber and a non-silicide etch step could be performed in another chamber.
Accordingly, an object of the invention includes using a unique combination of one or more of a preferred reactor configuration, wafer temperature and processing conditions to successfully meet the microelectronic integrated circuit fabrication requirements for silicides generally and cobalt silicide in particular.
The volatility problem with potential etch reaction products for cobalt makes the etchability of cobalt silicide similar in difficulty to platinum or iridium since these elements also have no known volatile reaction products at conventional etch process wafer temperatures. This invention teaches the use of the above reactor configurations, or other comparable reactors, the use of elevated wafer temperatures, the use of suitable hard mask materials, the process settings for gas chemistry, pressure, and RF power, and high speed changes in wafer temperature to etch each of the materials of a cobalt polycide stack. In particular the invention addresses the following in a variety of combinations:
1. The wafer temperature range, gas chemistry, pressure, and RF power, required to achieve high etch rate, and anisotropic etching of cobalt silicide with minimal etch rate and profile microloading.
2. The wafer temperature range to simultaneously meet all the etch requirements of both the cobalt silicide and polysilicon layers in the cobalt polycide stack.
3. The use of rapid wafer temperature changes, through a suitably designed wafer chuck to etch each layer in the cobalt polycide stack to meet all etch requirements.
4. The use of suitable hard mask materials to facilitate elevated wafer temperature etching and meet the mask requirements for etching cobalt polycide stack structures.
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U.S. patent application Ser. No. 09/760,402, Marks et al., filed Jan. 12, 2001.
DeOrnellas Stephen P.
Jerde Leslie G.
Marks Steven
Deo Duy-Vu
Fliesler Dubb Meyer & Lovejoy LLP
Tegal Corporation
Utech Benjamin L.
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