Synthetic resins or natural rubbers -- part of the class 520 ser – Synthetic resins – From silicon reactant having at least one...
Patent
1995-11-21
1998-11-24
Marquis, Melvyn I.
Synthetic resins or natural rubbers -- part of the class 520 ser
Synthetic resins
From silicon reactant having at least one...
528 42, 437231, 437243, C08G 7700
Patent
active
058408215
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method for evaluating siloxanes used for forming an insulating film which comprises determining the rates of structural units of siloxanes including, in particular, organic substituents directly bonded to Si atoms as a part of the structure thereof, present in a coating solution for forming an insulating film, i.e., a solution containing siloxanes which are used as precursors for forming an insulating film to level the surface of a substrate on which uneven portions are formed and to electrically insulate the substrate, in particular, an interlayer insulating film for leveling distributing wire structures of electronic devices such as an LSI multilevel interconnection structure and for insulating the multilevel interconnection structure, and evaluating the siloxanes on the basis of the rates thus determined; a coating solution for forming an insulating film, which comprises siloxanes and is used for producing a semiconductor device and a method for preparing the coating solution; and a method for forming an insulating film for semiconductor devices and a method for producing a semiconductor device using the insulating film-forming method.
BACKGROUND ART
Heretofore, the integration density of the semiconductor device has been increased, more finer and highly multilayered distributing wires for elements have correspondingly been required and, in turn, the steps formed between these distributing wires have increasingly been high. For this reason, the ability of an insulating material to fill up the gap formed between distributing wires and the surface flatness of an element after forming an insulating film have become serious problems. With regard to the tolerance in the flatness, the depth of focus of a resist becomes small for ensuring a desired resolution during the photolithography process and there has been reported that the unevenness of the surface of, for instance, a line-and-space pattern of 0.7 .mu.m should be limited to the level of not less than 200 nm. A chip or wafer must satisfy the foregoing requirement throughout the entire area thereof and therefore, the complete leveling of the chip or wafer throughout the entire area thereof is required according to its literal sense.
To solve these problems, there has presently been known a method for filling up steps on the surface of a substrate to thus level the surface through the formation of an insulating film by the chemical vapor deposition method using ozon and tetraethoxysilane as starting materials (O.sub.3 -TEOS AP-CVD), as disclosed in Japanese Un-Examined Patent Publication (hereinafter referred to as "J. P. KOKAI") No. Sho 61-77695.
The O.sub.3 -TEOS APCVD technique is excellent in the step coverage and can ensure excellent filling up properties, but the insulating film is formed in conformity with distributing wires and therefore, it is impossible to level the surface of a substrate over a wide area thereof. Moreover, the O.sub.3 -TEOS APCVD technique also suffers from a problem such that the rate of deposition observed on a wide flat portion differs from that observed on fine and dense distributing wire patterns and accordingly, it is difficult to flatten the surface of a pattern whose distributing wire density varies depending on the position.
In addition, there has also been known a method which comprises grinding the surface of a thick deposited insulating film by the chemical mechanical polishing (CMP) technique as disclosed in, for instance, L. B. Vines and S. K. Gupta, 1986 IEEE VLSI Multilevel Interconnect Conference, p. 506, Santa Clara, Calif. (1986) or R. Chebi and S. Mittal, 1991 IEEE VLSI Multilevel Interconnect Conference, p. 61, Santa Clara, Calif. (1991) or B. M. Somero, R. P. Chebi, E. U. Travis, H. B. Haver, and W. K. Morrow, 1992 IEEE VLSI Multilevel Interconnect Conf., p. 72, Santa Clara, Calif. (1992). It has been said that the CMP technique permits almost ideal leveling of the surface over a wide area if appropriately establishing the conditions for the CMP techni
REFERENCES:
patent: 4349609 (1982-09-01), Takeda et al.
patent: 4605446 (1986-08-01), Isozaki
patent: 4670299 (1987-06-01), Fukuyama et al.
patent: 4723978 (1988-02-01), Clodgo et al.
patent: 4798629 (1989-01-01), Wood et al.
patent: 4865649 (1989-09-01), Kashiwagi et al.
patent: 5043789 (1991-08-01), Linde et al.
patent: 5152834 (1992-10-01), Allman
patent: 5286572 (1994-02-01), Clodgo et al.
patent: 5401821 (1995-03-01), Geck et al.
Furusawa et al., "New Reflowable Organic Spin-On Glass for Advanced Gap-Filling and Planarization",Jun. 7-8, 1994, VMIC Conference, pp. 186-192.
Landon B. Vines et al., "Interlevel Dielectric Planarization with Spin-on Glass Films", (1986), 1986, V-MIC Conference, pp. 506-515.
R. Chebi et al., "A Manufacturable ILD Gap Fill Process With Biased ECR CVD", (1991) 1991 VMIC Conference, pp. 61-67.
B.M. Somero et al., "An Integrated, Low Temperature Interlayer Dielectric using ECR Technology for Advanced CMOS ASIC and Logic Applications", (1992), 1992 VMIC Conference, pp. 72-78.
Seitaro Matsuo et al., "Low Temperature Chemical Vapor Deposition Method Utilizing an Electron Cyclotron Resonance Plasma", (1983), Japanese Journal & Applied Physics, pp. L210-L213.
Katsuyuki Machida et al., "SiO.sub.2 Planarization Technology with Biasing and Electron Cyclotron Resonance Plasma Depositon for Submicron Interconnections", (1986), J. Vac. Sci. Technol. B 4 (4), pp. B4, 818-821.
SOG Technology, Oyo Butsuri, (Applied), (1988) vol. 57, No. 12, pp. 1931-1932.
Merk Index, p. 440, 9.sup.th ed. (1976).
M. P. Besland et al., "Silicon and Carbon Solid-State MASand Liquid-State MNR Study of the Polycondensation of Heteropolysiloxanes", Journal of the American Chemical Society, vol. 113, pp. 1982-1987, 1991.
Jan Pelnar et al., "Functional Group Identification by Two-Dimensional .sup.29pl Si NMR Spectroscopy with Reversed Detection and Signal Winnowing", Applied Technology, vol. 44, No. 3, pp. 396-400, 1990.
Nakano Tadashi
Ohta Tomohiro
Shimura Makoto
Kawasaki Steel Corporation
Marquis Melvyn I.
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