Coating device with As.sub.2 -O.sub.3 -SiO.sub.2

Details Coating device with As.sub.2 -O.sub.3 -SiO.sub.2 Coating device with As.sub.2 -O.sub.3 -SiO.sub.2

1981-05-05

1982-10-26

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 148187, 148188, 427 85, 427 93, H01L 2122, H01L 21283

Patent

active

043554547

ABSTRACT:
A method for fabricating a metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment, the fabrication processing includes forming a layer of arsenic doped glass as a multilevel interconnect system insulating layer. In another embodiment, the method includes the formation of a multilevel interconnect system insulating layer which includes the formation of a layer of undoped silicon dioxide as a barrier layer and then forming a layer of arsenic doped glass upon the undoped layer.

REFERENCES:
patent: 3571914 (1971-03-01), Lands et al.
patent: 3798081 (1974-03-01), Beyer
patent: 3825442 (1974-07-01), Moore
patent: 3972756 (1976-08-01), Nagase et al.
patent: 4013489 (1977-03-01), Oldham
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4224089 (1980-09-01), Nishimoto et al.
patent: 4270262 (1981-06-01), Hori et al.

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