Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-05-06
2003-12-09
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C331S044000
Reexamination Certificate
active
06661267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to phase-locked loops and more particularly to calibration circuits therefor.
2. Description of Related Art
Commonly assigned U.S. Pat. No. 5,508,660 of Gersbach et at for a “Charge Pump Circuit with Symmetrical Current Output for Phase-Controlled Loop System” shows a circuit which includes a charge pump connected between a phase comparator and a Voltage Controlled Oscillator (VCO). The output of the VCO is fed back in a phase-locked loop to the other input of the phase comparator. The phase comparator is connected to the feedback signal from the VCO and a source of a reference signal with a given input frequency. The output of the charge pump circuit is a current which is filtered by an RC filter that produces a control voltage based upon incrementing and decrementing signals received from the phase comparator. The control voltage across the RC filter is supplied to the input of the VCO. It is mentioned that a frequency divider can be interposed between the source of the reference signal, and the comparator, if desired. No means of calibration of the phase-controlled loop system is shown.
Commonly assigned U.S. Pat. No. 5,382,922 of Gersbach et at. for a “Calibration Systems and Methods for Setting PLL Gain Characteristics and Center Frequency” users two comparator inputs from a single filter voltage and performs a single pass calibration. There is a phase comparator connected to a source of a reference signal with a given input frequency. The output of the phase comparator is supplied to the input of a charge pump circuit. The output of the charge pump circuit is a current which is supplied in parallel to a calibration system and an RC filter that produces a control voltage based upon incrementing and decrementing signals from the charge pump. In this case, the output voltage from the filter is supplied to a Voltage-to-Current Converter VCC), the output of which is introduced to a summing node. The control voltage across the RC filter is supplied to the input of a VCO. The output of the VCO is fed back in a phase-locked loop to the other input of the phase comparator. The patent states that a frequency divider can be interposed between the source of the reference signal, and the comparator, if desired. The output of the calibration system is also supplied to the summing node. The output of the summing node is supplied to an oscillator which together with the voltage-to-current converter comprises a VCO. The calibration system includes calibration logic which receives inputs from a pair of comparators and produces an up signal when the control voltage is greater than a second reference voltage and a down signal when the control voltage is less than a first reference voltage. When the calibration cycle has resulted in the “High Order Counter Bits Unchanged For n Cycles”, then the “calibration complete signal is issued . . . and processing terminates . . . ” That is to say that the calibration is not continuous. The patent also states “Automated, repeated calibration of the PLL circuit is anticipated using the integrated, digital circuits described. An optimal voltage-frequency point is attained by the repeated calibration of the PLL to a center, steady state frequency.”
The problem with the stopping of the cycle of calibration and then automated repeating of the process is that with the systems taught in the prior art, each time the calibration cycle is started, the system cannot handle data because of the jitter of the VCO during the intermittent or one time calibration process.
Commonly assigned U.S. Patent No. 6,175,282 of Yasuda for “Method for Calibrating a VCO Characteristic and Automatically Calibrated PLL Having a VCO” claims calibrating an oscillation frequency versus a control voltage characteristic of a VCO in which an oscillation frequency is changed in responsive to a control voltage, performing a calibration to establish an oscillation frequency in the VCO at a maximum target frequency value when a control input to the VCO reaches a reference voltage, and verifying that the control voltage is within an operating range when the oscillation frequency is established at a minimum target frequency value. The flow chart of the calibration process of Yasuda also ends two steps after the reference frequency is less than the control voltage, at the point at which “the oscillation frequency of is actually reduced to the lowest value ft L of the target frequency of the VCO . . . ”, i.e. “fo=ft_L” and the flow chart indicates that the process ends at that point. There is no suggestion of a repetition of the process to maintain continuous calibration.
Additional references include U.S. Pat. No. 5,027,087 of Rottinghans for “Fast-Switching Frequency Synthesizer”; U.S. Pat. No. 5,625,325 of Rotzoll et al. for “System and Method for Phase Lock Loop Gain Stabilization”; U.S. Pat. No. 5,686,864 of Martin et al. for “Method and Apparatus for Controlling a Voltage Controlled Oscillator Tuning Range in a Frequency Synthesizer”; U.S. Pat. No. 5,909,149 of Bath et al. for “Multiband Phase Locked Loop Using a Switched Voltage Controlled Oscillator; and U.S. Pat. No. 5,942,949 of Wilson et al. for “Self-Calibrating Phase-Lock Loop with Auto-Trim Operations for Selecting an Appropriate Oscillator Operating Curve”.
SUMMARY OF THE INVENTION
An object of this invention is to provide a system including a comparator circuit and calibration circuit which solve the problem of having to deal with Voltage Controlled Oscillator (VCO) frequency (“speed”) drift due to temperature, voltage, and other environmental variations during operation. The dynamic nature of the DCC circuit of this invention functions better than static circuits that attempt to compensate for environmental changes.
To solve the problems of such variations, an object of the present invention is to provide a system capable of continuous recalibration of the PLL without causing errors due to jitter.
In accordance with this invention, a calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump receives an error signal from the phase/frequency detector and provides a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output indicating when the polarity of the error signal exceeds a positive or negative limit. A calibration means for continuously providing incremental calibration inputs to the VCO after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.
Preferably, the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator. The calibration means begins a calibration cycle by sampling the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time. The calibration means determines whether the calibration has corrected a detected error and repeats the correction cycle until correction of the error has been detected followed by returning to the beginning of the calibration cycle.
Preferably the VCO comprises a voltage to current (V-I) converter connected to provide an input to a current controlled oscillator (ICO), and the calibration means includes a Dynamic Course Correction (DCC) circuit and a Digital to Analog Converter (DAC) and the DAC provides an input to the ICO.
Preferably, the DAC includes means delaying the rate of change of incremental calibration input to the ICO.
Glossary
BIST Built-In Self Test
CALCOMP Calibration Comparators System including a set of three analog comparators that lock at the differential fi
Moy Victor
Mullgrav, Jr. Allan Leslie
Sorna Michael A.
Walker Norman Hugo
Cox Cassandra
Jones II Graham S.
Schnurmann H. Daniel
Wells Kenneth B.
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