Co-processor combination

Details Co-processor combination Co-processor combination

1983-01-17

1986-05-20

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900

Patent

active

045905568

ABSTRACT:
A dual processor system in which one processor is dedicated to input/output tasks while the other is dedicated to high level language tasks when operating as a 16-bit machine. The processors include a first microprocessor which is an 8-bit machine, and a second microprocessor which is a 16-bit machine. The first processor has a memory associated therewith which may, for example, be a 64K memory while the second processor has a larger capacity memory. The second processor does not access the memory of the first processor, however, the first processor can access a portion of the second processor's memory. Access to the second processor's memory is controlled by an arbitrator that is operated by system software to prevent access conflicts. For boot-up during power-up operation, a boot ROM is used, attached to the 8-bit processor having stored therein a boot strap program that is initially loaded into the 8-bit processor memory. If the operating system loaded from a diskette indicates 8-bit software, then the 16-bit processor is maintained reset or halted. On the other hand, if the operating system is a 16-bit system, then the boot program loads the 16-bit memory making the 16-bit processor the main processor. The 8-bit processor then functions as an I/O processor. This boot-up procedure allows the 8-bit processor to turn on first and makes the system initially appear as an 8-bit processor system. In this way the system is compatible with software written for an 8-bit machine even though the system is normally run and identified as a 16-bit machine.

REFERENCES:
patent: 4073005 (1978-02-01), Parkin
patent: 4415972 (1983-11-01), Adcock
patent: 4443846 (1984-04-01), Adcock
patent: 4462086 (1984-07-01), Kurakake

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