Co-planar well-type charge coupled device with enhanced storage

Details Co-planar well-type charge coupled device with enhanced storage Co-planar well-type charge coupled device with enhanced storage

1977-08-26

1982-12-14

Munson, Gene M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307221D, 365183, 357 91, H01L 2978, G11C 1928, G11C 1134

Patent

active

043640761

ABSTRACT:
A charge coupled device memory is disclosed which includes a plurality of stages having increased charged storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under the phase electrodes is divided into barrier regions and adjacent well regions bounded by the channel. A dopant layer of a second-type conductivity lies in each of the well regions relatively near to the first surface. An enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions relatively far from the surface having a doping which is greater than the doping of the first-type conductivity semiconductor substrate.

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patent: 4103347 (1978-07-01), Barton
patent: 4110777 (1978-08-01), Esser et al.

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