CN.sup.2 test pattern generator

Details CN.sup.2 test pattern generator CN.sup.2 test pattern generator

1987-08-14

1989-07-25

Ruggiero, Joseph

Excavating

371 21, G01R 3128

Patent

active

048520969

ABSTRACT:
A CN.sup.2 memory testing circuit for generating a sequence of C(N.sup.2 +1) memory addresses which will accomplish a CN.sup.2 test with the least possible memory transitions. In one embodiment for an odd integer C, the mth bit in the memory address sequence comprises at least one repetition of a unique transition bit (UTB) pattern, where the UTB pattern comprises

REFERENCES:
patent: 4263669 (1981-04-01), Staiger
patent: 4429389 (1984-01-01), Catiller
patent: 4442519 (1984-04-01), Jones
patent: 4754215 (1988-06-01), Kawai
patent: 4763375 (1988-04-01), Tannhauser

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