Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-12-13
2001-06-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S110000, C438S113000, C438S114000, C438S127000
Reexamination Certificate
active
06251703
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to micro-electronic circuit technology, more particularly to the technology known as Chip Scale Packaging (“CSP”) in which the final component extends over a surface which does not exceed the size of the integrated circuit chip. In other words, the coating over the chip does not increase the surface area occupied by the component on the substrate that will receive it. CSP technology is particularly advantageous in the fields where the miniaturization of the circuits is an essential parameter, such as in pacemaker circuits and other active implantable medical devices.
BACKGROUND OF THE INVENTION
CSP techniques are known. One technique is described in WO-A-93/24956, whose applicant is a co-assignee of the present invention, and which reference describes a method of manufacture of a component in which the face of the chip is completely covered with a layer of a resin coating and carries a series of metalizations connected to the contact pads of the chip, these pads beings embedded in the resin layer. The technique described in this document makes it possible to obtain a collective coating which is applied to the semiconductor wafer before the wafer is cut into chips, which technique minimizes the unit cost applied to each chip. However, in this technique, the resin coating covers the entirety of the wafer, which can generate two types of difficulties. First, the wafers produced today are increasing in size, the diameters of which have evolved from 4, 5, 6, 8 and up to 12 inches, and the total constraint generated on the wafer by the hardening of the resin, which is very hard once polymerized, can stress this wafer, and even cause cracks, breaks or cleavages. Second, the resin is in contact with the active part of the electronic circuits etched or formed on the various chips and can, in the long run, allow ionic contamination or various chemical pollutants permeate through the resin. Indeed, unlike the “chip carrier technologies”, wherein the chip is completely insulated in a sealed case filled with a neutral gas such as nitrogen, the resin constitutes only an impediment, not a barrier, to the aggressions of the external medium, and consequently can reduce the long-term reliability of the electronic micropattern, which is not completely isolated.
OBJECT AND SUMMARY OF THE INVENTION
It is an object of the present invention to propose a method for realization of a component in CSP technology, making it possible to cure the aforementioned disadvantages. The process remains a collective process, applicable to the wafer before the wafer is cut into chips, so as to preserve a competitive manufacturing cost.
The process of the invention is of the general type indicated above, namely a collective process applied to a wafer carrying a plurality of individual chips formed therein, and from which will be formed, after the wafer is cut, a corresponding plurality of components, the resulting components each being a “CMS” component of the CSP type, having a surface with dimensions extending a length and a width that is appreciably the same dimensions as the dimensions of the chip that it incorporates.
According to the invention, one embodiment of the process is characterized by the steps of:
(a) obtaining a wafer on which the aforementioned plurality of individual chips are formed, e.g., etched, with, for each chip, a series of contact pads laid out on at least one of the sides of the chip;
(b) sealing on this wafer, in predetermined areas of each component, a cap, the cap comprising an opening for each pad of the subjacent chips, these openings being through-holes authorizing an access to the corresponding pads;
(c) forming in the cap, in a fraction of its thickness, of trenches following the sides, or respectively the peripheries, of each subjacent chip, with the various openings all emerging in a trench;
(d) establishing electrically conducting connections to the pads through the openings, these electrical connections emerging from the top face of the cap;
(e) flowing a resin coating into the openings and the trenches;
(f) polishing and metalizing the cap; and
(g) cutting the wafer into individual components.
In a preferred embodiment, the cap is a wafer that is comparable in nature to and of the same dimensions as the wafer on which the chips are etched, more particularly a silicon wafer. The phrase “comparable in nature” is used to mean a material having substantially the same coefficient of expansion and contraction and rigidity.
The sealing step (b) is preferably performed by depositing or engraving an adhesive strip along the periphery of each chip, and possibly, also depositing an adhesive material into the central area of each chip, to provide that the cap is securely affixed to each chip when the wafer is cut.
In one embodiment, installing the electrically conducting connections at step (d) is obtained by welding or soldering (collectively “welding”) metal wire onto the pads through the openings, and/or forming metal conductors by deposition and etching of a metalization in contact with the pads, and extending the contact over the sides and out from the openings, and from the bottom and the sides of the trenches, such that the metalization is electrically isolated from the wafer and the cap. Alternatively, the conducting electric connections installed at step (d) emerge at the surface of the cap in the form of contacts distributed in the periphery of the component, and/or points of a pattern for interconnection leading to contacts distributed in the central area of the component.
It should be understood, however, that the invention also is directed to a CMS (also known as surface mount technology “SMT”) component of the generic type having a chip comprising an external coating allowing its connection to a substrate, this coating bearing on its surface a plurality of external metallizations electrically connected, through the coating material, to the pads of the chip, the component being a component of the CSP type having, in the length and width dimensions, appreciably the same dimensions as those of the chip before coating.
According to this aspect of the invention, this component is characterized in that the chip is covered on its surface with a cap sealed to the chip in predetermined areas, this cap comprising openings over each subjacent contact pad, these openings being through-holes authorizing an access to the corresponding pads, and also comprising a network trench formed in a fraction of the cap thickness along at least one of the sides of the component carrying the pads, the various openings all emerging in a trench, and in that the resin coating is formed on the cap and on a reduced thickness of the surface, essentially in the region of the trench.
The cap can be in particular a wafer comparable in nature to, and of the same dimensions as, the wafer on which the chips are etched, in particular a silicon wafer. In addition, the cap can be sealed by an adhesive strip defining in the periphery of each chip, and possibly, also an adhesive deposited in the central area of each chip.
REFERENCES:
patent: 4613891 (1986-09-01), Ng et al.
patent: 5554887 (1996-09-01), Sawai et al.
patent: 5714800 (1998-02-01), Thompson
patent: 5858815 (1999-01-01), Heo et al.
patent: 5926380 (1999-07-01), Kim
patent: 6057597 (2000-05-01), Farnworth et al.
patent: 6109369 (2000-08-01), Crumly et al.
patent: 10012765 (1998-01-01), None
patent: WO 98/33211 (1997-01-01), None
XP-002113822 Val C.M: “New Chip Scale Package for Medical Applications: “Plip-Chip”” Proceedings 1996 International Symposium on Microelectronics, pp. 236-242.
Bono Hubert
Campenhout Yves Van
Gilet Dominique
Legay Thierry
ELA Medical S.A.
Jones Josetta I.
Niebling John F.
Orrick Herrington & Sutcliffe LLP
LandOfFree
CMS coated microelectronic component and its method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CMS coated microelectronic component and its method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMS coated microelectronic component and its method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2544545