Abrading – Precision device or process - or with condition responsive... – By optical sensor
Reexamination Certificate
2000-02-02
2002-04-02
Banks, Derris H. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
By optical sensor
C451S041000, C451S287000
Reexamination Certificate
active
06364744
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and, more particularly, to planarizing or polishing semiconductor wafer surfaces during the manufacture of integrated circuits.
BACKGROUND OF THE INVENTION
Semiconductor devices, also called integrated circuits, are mass produced by the fabrication of identical circuit patterns on a single semiconductor wafer. During the process, the wafer is cut into identical dies or chips. Although commonly referred to as semiconductor devices, the devices are fabricated from various materials, including conductors (e.g. copper, aluminum and tungsten), non-conductors (e.g. silicon dioxide) and semiconductors (e.g. silicon). Silicon is the most commonly used semiconductor, and is used in either its single crystal or polycrystalline form. Polycrystalline silicon is often referred to as polysilicon or “poly”. The conductivity of the silicon is adjusted by adding impurities in a process commonly referred to as doping.
Within an integrated circuit, thousands of devices (e.g., transistors, diodes) are formed. Typically, contacts are formed where a device interfaces to an area of doped silicon. Specifically, plugs are typically formed to connect metal layers with device active regions. Vias are typically formed to connect metal layers with other metal layers. Also interconnects are typically formed to serve as wiring lines to interconnect the many devices on the integrated circuit and the many regions within an individual device. These contacts and interconnects are formed using conductive materials.
The integrated circuit devices with their various conductive layers, semiconductive layers, insulating layers, contacts and interconnects are formed by fabrication processes, including doping processes, deposition processes, photolithographic processes, etching processes and other processes. At certain steps, it is often desirable to achieve a pre-determined level of surface planarity, uniformity, and/or roughness. It is also desirable to minimize surface defects such as pits and scratches. Such surface irregularities may affect the performance of the final semiconductor device and/or create problems during subsequent processing steps.
One common technique to planarize a wafer is known as chemical mechanical polishing (CMP). CMP is very widely used technique which delivers a slurry of material to the wafer surface and while a polishing pad or belt is passed over the wafer surface. The slurry typically includes a plurality of abrasive particles dispersed in a liquid. For example, U.S. Pat. No. 5,728,308 entitled “Method of polishing a semiconductor substrate during production of a semiconductor device” discloses a conventional slurry used for chemical mechanical polishing including abrasive particulates comprised of metal oxides such as silica (SiO
2
), alumina (Al
2
O
3
), titanium oxide (TiO
2
), and cerium oxide (CeO
2
) of a particle size of about 10 nm in an aqueous solution of potassium hydroxide (KOH).
Typical slurries also include stabilizers, one or more oxidizing and/or complexing agents, and a suspension agent or surfactant. A conventional surfactant, or surface wetting agent, may include an emulsion comprising mostly water, and also include fat/oils and alcohols/iso-alcohols, for example. The fat/oil serves to keep the abrasive particles in suspension.
A semiconductor wafer typically includes a dielectric layer and numerous metal layers which may include tungsten, aluminum, copper, tantalum, titanium, titanium nitride, tantalum nitride or any other metal commonly used in the production of integrated circuits. In conventional CMP processes for polishing metal layers of a wafer, metal removal rates are limited by the rate of metal oxidation. Therefore, typical slurries include oxidizers to oxidize the metal because the metal oxides polish faster compared to the pure metal. Also, for CMP of copper layers, for example, because metal removal rates are limited by the rate of metal oxidation, corrosion inhibitors are necessary in the slurry to prevent corrosion of the copper layer before oxidation.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to enhance the removal rates of CMP for metal layers of the semiconductor wafer.
It is another object of the present invention to provide a slurry which does not require corrosion inhibitors for CMP.
These and other objects, features and advantages in accordance with the present invention are provided by a chemical mechanical polishing (CMP) system for polishing a semiconductor wafer including metal. The system comprises a polishing device including a polishing article support, and a polishing article held by the polishing article support for relative movement with the semiconductor wafer. A slurry is provided at an interface between the polishing article and the semiconductor wafer, and the slurry comprises abrasive particles and at least one mixed metal oxide to enhance oxidation of the metal of the semiconductor wafer. The system preferably includes a light source providing light at the interface between the polishing article and the semiconductor wafer. The slurry may include water and the at least one mixed metal oxide is a photocatalyst for breaking down water into hydrogen and oxygen in the presence of light.
The light provided by the light source is preferably ultraviolet and the light source may be positioned adjacent the polishing article support opposite the polishing article. Thus, at least portions of the polishing article support and the polishing article may be transparent. Also, the light source may be carried by the polishing article support.
The at least one mixed metal oxide preferably comprises at least one of SrTiO
3
, CeTiO
3
, BaTiO
3
, and (Sr
x
Ba
1−x
)TiO
3
and may include an NiO coating. The slurry may be acidic with the at least one mixed metal oxide being soluble in the slurry. Alternatively, the slurry may be alkaline with the mixed metal oxide being insoluble in the slurry. Here, the mixed metal oxide may comprise abrasive particles.
The objects, features and advantages in accordance with the present invention are also provided by a method of chemical mechanical polishing a semiconductor wafer including metal. The method including the steps of providing relative movement between the semiconductor wafer and a polishing article, providing light at the interface between the polishing article and the semiconductor wafer, and delivering a slurry to the interface between the semiconductor wafer and the polishing article. The slurry preferably comprises abrasive particles and at least one photocatalyst to enhance oxidation of the metal of the semiconductor wafer. The slurry further comprises water, and the photocatalyst comprises a mixed metal oxide for breaking down water into hydrogen and oxygen in the presence of light.
REFERENCES:
patent: 5728308 (1998-03-01), Muroyama
patent: 5775980 (1998-07-01), Sasaki et al.
patent: 5879226 (1999-03-01), Robinson
patent: 5916855 (1999-06-01), Avanzino et al.
patent: 6159073 (2000-12-01), Wiswesser et al.
patent: 6177026 (2001-01-01), Wang et al.
Merchant Sailesh Mansinh
Misra Sudhanshu
Roy Pradip Kumar
Agere Systems Guardian Corp.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
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