CMP process

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Reexamination Certificate

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C438S694000, C438S695000

Reexamination Certificate

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06844262

ABSTRACT:
A method of making a semiconductor structure includes determining a polish time which is sufficient to planarize a layer on a semiconductor substrate. The layer is polished for the polish time to planarize the layer, and then the layer is polished to a predetermined thickness. The semiconductor structures can be used to make a semiconductor device.

REFERENCES:
patent: 5830041 (1998-11-01), Takahashi et al.
patent: 6186877 (2001-02-01), Lofaro
patent: 6351723 (2002-02-01), Maekawa
patent: 6476921 (2002-11-01), Saka et al.
patent: 6484300 (2002-11-01), Kim et al.
F. Preston,J. Soc. Glass Tech.(1927) 11:214-256.
Encyclopedia of Chemical Technology, Kirk-Othmer, vol. 14, pp. 677-709 (1995).

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