CMP process

Details CMP process CMP process

2001-08-20

2004-11-23

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S693000, C216S017000

Reexamination Certificate

active

06821894

ABSTRACT:

The invention relates to a metal CMP process in conjunction with the contact hole or metal track etching. The metalization layers used in this case may be composed for example of tungsten or copper.
In electronic components, connections between metal track planes generally comprise so-called W or tungsten contacts. The latter are produced as follows: after the patterning of the contact holes, a liner generally composed of titanium and titanium compounds (e.g. TiN) is applied over the whole area and a metalization layer made of tungsten is subsequently applied to the dielectric. Afterward, the applied material is removed in regions in a CMP process (chemical mechanical polishing process). This CMP step stops on the dielectric in which the patterned portions are present. The tungsten-filled contact holes remain. The same is similarly true for a copper metalization layer or other metalization layer in which both the contact holes and the interconnect are patterned before the metal deposition into the dielectric.
The procedure according to the prior art is associated with various problems:
A high defect density results due to CMP scratches, said density depending on how long the dielectric is polished.
The alignment markers of the lithography are significantly eroded, which can lead to overlay errors.
As a result of excessively short polishing in the CMP process, metal residues in the following metal plane can lead to short circuits.
Defects in underlying planes (e.g. scratches, holes) are mapped in the dielectric and are filled with metal. This metal can only be removed with difficulty in the CMP step and later leads to short circuits.
The disadvantages listed are aggravated by the fact that the end point identification of the CMP process is unreliable. If the dielectric has a residual topology, then this results in further disadvantages since a longer polishing time becomes necessary.
Methods of this type can also be applied to an interconnect plane, the so-called damascene technique being used. In this document, the technical subject matter is essentially described with reference to contact holes.
The invention is based on the object of providing an improved CMP process.
The invention is based on the insight that the CMP process can be significantly improved by means of a suitable auxiliary layer which is applied to the dielectric before the contact hole or metal track etching. The auxiliary layer, which can be etched wet-chemically without any residues due to the oxidizing conditions during the metal CMP process or can be removed to a great extent by the polishing, reduces excessive processing of the surface of the dielectric.
The auxiliary layer is preferably formed with a thickness of 20 to 100 nm. It is preferably composed of diamond-like carbon, carbon polymers or of other porous materials. What is crucial is the easy and residue-free removal in the CMP process. The oxidizing conditions in a metal CMP process are produced, for example, by the following substances: Fe(NO
3
)
3
, H
2
O
2
, KIO
4
.
The possibility of undercutting the liner as soon as the latter is perforated in the CMP process means that the liner itself can be polished away significantly more quickly in the surroundings. Overall, this leads to the following advantages:
The liner is removed more reliably and more quickly, which shortens the time for the CMP process. As a direct consequence of this, the time of overpolishing on the dielectric is reduced, as a result of which the defect density directly decreases. Another advantage that should be mentioned in this connection is that the edge rounding of alignment markers is greatly reduced, thereby enabling more reliable and more accurate alignment of the photomask for patterning the next metal plane.
In the case of an existing topology in or on the dielectric, the risk of liner residues in deeper regions can be considerably reduced. This is based on the elevation of the liner and of the metalization layer by the underlying auxiliary layer. Consequently, the liner and the metalization layer can be encompassed by the CMP process in particular in superficial depressions of the dielectric.
If local topologies are transferred through defects from deeper planes, then they are filled with the auxiliary layer instead of with metal.
This can prevent metal residues, which would later lead to short circuits, from remaining at these locations.
Furthermore, the patternability of the next metal planes can be positively influenced in that the height by which an interconnect or the contact hole projects beyond the dielectric is reduced. This is to be seen in connection with a lower defect density after the metal CMP process, and, in the subsequent so-called touchup, the quantity of oxide to be removed is reduced.
Preferably, an additional wet-chemical cleaning step can be added if residues of the auxiliary layer have to be removed. This cleaning step can be combined in a simple manner with the obligatory brush cleaning after the CMP process or the wet-chemical postcleaning.
An advantageous refinement of the invention provides for the auxiliary layer to be used as a hard mask for the contact hole patterning by means of dry etching. This is done before the CMP process, resulting in multiple utilization of the auxiliary layer. In conjunction with a CARL resist, such an auxiliary layer can equally be used as a replacement for a bottom resist as a hard mask for the patterning of contact holes. Consequently, there is no cost disadvantage due to an additional layer.


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patent: 0 696 819 (1996-02-01), None
patent: WO 99/33102 (1999-07-01), None

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