CMOS Window detector with hysteresis

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307359, 307363, H03K 5153

Patent

active

045033404

ABSTRACT:
A CMOS window detector provides an output signal which indicates the relationship of an input signal to a voltage "window" as a function of the previous output signal. The window detector includes first and second current source circuits and first and second inverter circuits. A bias current is established in each current source circuit as a function of a different reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FET of each inverter circuit is connected to its respective current source circuit and establishes a current in the inverter current path equal in magnitude to its respective bias current. The input signal is applied to the gates of the current control FETs. Each current control FET changes conductivity state when the input signal reaches the reference voltage level used to establish the respective inverter current flow. Each reference voltage therefore represents a window voltage level. The difference in window voltage levels defines the voltage window. An output circuit formed by a CMOS NAND-latch is connected to the first and second inverter circuits and provides the output signal which exhibits hysteresis with respect to the input signal.

REFERENCES:
patent: 3609411 (1971-09-01), Ma et al.
patent: 3809926 (1974-05-01), Young
patent: 3984703 (1976-10-01), Jorgensen

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