CMOS whole chip low capacitance ESD protection circuit

Details CMOS whole chip low capacitance ESD protection circuit CMOS whole chip low capacitance ESD protection circuit

2001-12-04

2004-02-10

Toatley, Jr., Gregory J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C257S173000, C257S355000

Reexamination Certificate

active

06690557

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90123428, filed Sep. 24, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
This present invention relates to an electrostatic discharge protection circuit More particularly, the present invention relates to a low capacitance electrostatic discharge protection circuit for a built CMOS chip.
2. Description of Related Art
Electrostatic discharge (ESD) during or after fabrication is one of the major causes of damage for an integrated circuit (IC) such as dynamic random access memory (DRAM) and static random access memory (SRAM). A person walking on a carpet produces a static voltage ranging from a few hundred to a few thousand volts when the relative humidity (RH) of the surrounding air is high. If the relative humidity is really low, an electrostatic voltage exceeding ten thousand volts may be produced. IC packaging machines or IC testers may also generate a static voltage ranging from a few hundred to a few thousand volts depending on surrounding temperature and humidity
When these conductive bodies contact a silicon chip, electrostatic charges may be released through the chip leading to a failure of internal integrated circuits. To prevent any damages to the integrated circuits due to an ESD, various methods are developed.
FIG. 1
is a diagram showing a conventional ESD protection circuit. As shown in
FIG. 1
(also refer to U.S. Pat. No. 4,896,243), a lateral silicon controlled rectifier (LSCR)
102
is used to protect an input buffer
104
against damages due to ESD. As an ESD event enters through a bonding pad
106
, the voltage created by an ESD source is higher than the triggered voltage of the LSCR
102
. The LSCR
102
conducts permitting the flow of a bypass current. Hence, ESD current is prevented from passing into the buffer
104
to cause any damages.
FIG. 2
is a graph showing the current-voltage relationship of the LSCR in FIG.
1
. As shown in
FIG. 2
, an operating voltage VDD applied to the anode node of the LSCR
102
will not lead to the turn-on of the LSCR
102
. Hence, no leakage current flows in the LSCR
102
. On the other hand, as an ESD voltage having a voltage higher than the triggered point (the triggered voltage such as 50V in
FIG. 2
) is applied to the anode, the LSCR
102
conducts and permits the majority of the ESD current to bypass. As the LSCR
102
is triggered on, the LSCR
102
steps into a holding region where a voltage drop of just 1V exists between the anode node and the cathode node of the LSCR
102
.
Aside from using LSCR as device for conducting an electrostatic discharge bypass, other devices includes modified lateral silicon controlled rectifier (MLSCR) and low-voltage trigger lateral silicon controlled rectifier (LVTSCR) may be used.
FIG. 3
is a graph showing the current-voltage relationship of a MLSCR. As shown in
FIG. 3
(refer to U.S. Pat. No. 4,939,616), an operating voltage VDD applied to the anode node of the MLSCR will not lead to the turn-on of the MLSCR. Hence, no leakage current flows in the MLSCR. On the other hand, as an ESD voltage having a voltage higher than the triggered point (the turn-on voltage such as 25V in
FIG. 3
) is applied to the anode node, the MLSCR conducts and permits majority of the ESD current to bypass. As the MLSCR is triggered on, the MLSCR steps into a holding region where a voltage drop of just 1V exists between the anode node and the cathode node of the MLSCR. Since the MLSCR has a lower triggered voltage than the LSCR, MLSCR permits ESD at a lower voltage. Hence, MLSCR provides more effective protection for input buffers gate oxide (may also protect output buffers and other internal circuits as well).
FIG. 4
is a graph showing the current-voltage relationship of a LVTSCR. As shown in
FIG. 4
(refer to U.S. Pat. No. 5,465,189), an operating voltage VDD applied to the anode node of the LVTSCR will not lead to the turn-on of the LVTSCR. Hence, no leakage current flows in the LVTSCR. On the other hand, as an ESD voltage having a voltage higher than the triggered point (the turn-on voltage such as 10V in
FIG. 4
) is applied to the anode node, the LVTSCR conducts and permits majority of the ESD current to bypass. As the LVTSCR is triggered on, the LVTSCR steps into a holding region where a voltage drop of just 1V exists between the cathode and anode of the LVTSCR. Since the LVTSCR has a triggered voltage lower than the LSCR and the MLSCR, the LVTSCR permits ESD at a lower voltage still. Hence, the LVTSCR provides even more effective protection for input buffers gate oxide (it may also protect output buffers and other internal circuits as well).
The SCR (such as LSCR, MLSCR or LVTSCR) used inside an ESD protection circuits occupies relatively small chip area and provides very high voltage protection. However, the SCR may be triggered into a turned-on state due to noise leading to the passage of current into the ESD protection circuit unnecessarily. Furthermore, since the holding voltage once the SCR is turned on is much lower than its normal operating voltage, the SCR may produce a large leakage current.
In addition, due to dimensional requirements of semiconductor fabrication, breakdown voltage of the gate oxide layer of the MOS transistor for an input buffer and the junction between voltage of an output buffer is gradually lowered. Because the LSCR or the MLSCR has a relatively high triggered voltage, the LSCR or the MLSR may not be turned on fast enough to protect the input and output buffers against any damages when an ESD occurs. Although the LVTSCR has a lower triggered voltage, internal circuits may still be damaged by ESD if no control circuit is used to reduce triggered voltage further because long metal routing layout will cause much RC delay. Since most internal circuit devices are fabricated according to the smallest design rules and the carrier chip increasingly miniaturized, damages to internal circuits due to non-effective ESD protection is likely to cause more problems.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a low capacitance electrostatic discharge (ESD) protection circuit for a CMOS whole chip. The protection circuit utilizes a control circuit to produce a substrate-triggered design so that silicon controlled rectifier (SCR) triggered voltage is effectively reduced and turn-on efficiency of the ESD protection circuit is increased. Furthermore, holding voltage of the SCR is also raised so that a large leakage current due to latching when SCR is accidentally triggered on is prevented. Hence, the ESD protection circuit provides full protection of the silicon chip. In addition, the protection circuit employs a low input capacitance design so that the chip protection circuit can be used inside high frequency or radio frequency circuits as well.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a low capacitance electrostatic discharge (ESD) protection circuit for a CMOS whole chip. The ESD protection circuit protects internal circuits of the silicon chip. A first voltage source and a second voltage source are applied to the ESD protection circuit. The ESD protection circuit is coupled to a bonding pad and an internal circuit. The ESD protection circuit includes a first diode series, a second diode series, a first control circuit, a third diode series, a first silicon controlled rectifier (SCR), a second control circuit, a fourth diode series and a second silicon controlled rectifier (SCR). The negative terminal of the first diode series is coupled to the first voltage source. The positive terminal of the first diode series is coupled to the bonding pad. The negative terminal of the second diode series is coupled to the positive terminal of the first diode series and the positive terminal of the second diode series is coupled to the second voltage source. A first terminal of the first control circuit is couple

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