CMOS voltage shifter

Details CMOS voltage shifter CMOS voltage shifter

2000-06-30

2002-07-09

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S068000

Reexamination Certificate

active

06417716

ABSTRACT:

TECHNICAL FIELD
This invention relates to a CMOS voltage shifter, and more particularly a shifter including a differential cell circuit operational when supplied with a low high supply reference voltage.
BACKGROUND OF THE INVENTION
Voltage shifters are used for many applications, especially in integrated circuits, to raise or lower a supply voltage of a relatively low value (typically 3.3V to 5V), as appropriate for circuitry connected to that supply voltage.
A conventional differential cell voltage shifter
1
is illustrated generally by the diagram of FIG.
1
.
The voltage shifter
1
is supplied a relatively high voltage reference VDDHIGH, e.g., above the maximum voltage that can be applied to a MOS transistor.
In particular, the high voltage reference VDDHIGH is supplied to a first pair of P-type MOS transistors MP
1
and MP
2
, which are cross-connected together so as to have their respective gate and drain terminals connected to the source terminals of a second pair of P-type MOS transistors MP
3
and MP
4
. The gate terminals of the second transistor pair MP
3
, MP
4
receive a reference voltage VREF which is generated locally.
The second pair of transistors MP
3
and MP
4
have their drain terminals connected to respective source terminals of a pair of N-type MOS transistors MN
1
and MN
2
, the gate terminals of which are driven respectively by an input signal VIN presented on an input terminal IN of the voltage shifter
1
, and its inverse provided by an inverter INV which is connected between the input terminal IN and the gate terminal of the transistor MN
2
. The voltage shifter
1
also has an output terminal OUT which is coincident with the source terminal of the transistor MN
2
.
The NMOS transistors MN
1
and MN
2
are drift transistors, that is, transistors which are formed to accept a high voltage value, such as VDDHIGH, on their drain terminals only, without involving any alterations of the process steps or the masks used for manufacturing standard MOS transistors.
As shown in
FIG. 1
, a reference voltage VREF is set by a divider, formed of first and second P-type MOS transistors MP
5
and MP
6
, which are connected in series with each other in a diode configuration between the high voltage reference VDDHIGH and a ground reference GND.
Where these transistors MP
5
, MP
6
are selected identical with each other, a value of the reference voltage VREF is obtained which is one half the value of the high voltage VDDHIGH, namely:
VREF=VDDHIGH/
2  (1)
The different conditions of operation of the voltage shifter
1
will now be discussed.
When the value of the input signal VIN to the input terminal IN is same as or near that of the ground reference GND, the drain terminals of the transistors MP
1
and MP
2
are at VDDHIGH, and the drain terminals of the transistors MP
3
and MP
4
are at GND and VDDHIGH+Vth(MP
4
), respectively, with Vth(MP
4
) being the threshold voltage value for the transistor MP
4
.
The terminals of all PMOS transistors exhibit a voltage drop of VDDHIGH+Vth(PMOS), with Vth(PMOS) being the threshold voltage value of a PMOS transistor. This value normally is adequate to power the transistors in question. Otherwise, additional cascode stages, that is, additional pairs of PMOS transistors in the same configuration as the transistors MP
3
and MP
4
, would have to be introduced.
Further, the drain terminal of the transistor MN
1
is at VDDHIGH. This value can only be accepted because drift NMOS transistors are used instead of standard NMOS transistors.
When the input signal VIN to the input terminal IN is changed, from a value near GND to a value equal to a further supply voltage reference VDDLOW of lower value than VDDHIGH, the drain terminal of the transistor MN
1
is taken down to GND and the source terminal of the transistor MP
3
up to a value of VREF+Vth(MP
3
), with Vth(MP
3
) being the threshold voltage value of the transistor MP
3
. As the voltage value across the gate and source terminals of the transistor MP
3
drops below the threshold voltage Vth(MP
3
) thereof, the transistor MP
3
is turned off.
Likewise, as the voltage value of VDDHIGH−VREF+Vth(MP
3
) across the gate and source terminals of the transistor MP
2
rises above the threshold voltage Vth(MP
2
) thereof, this transistor is turned on, and the voltage value at the output terminal OUT of the voltage shifter
1
is taken up to the high voltage value VDDHIGH.
The maximum voltage drop across the terminals of the PMOS transistors comprising the voltage shifter
1
is of VDDHIGH+Vth(PMOS), even under this condition of their operation.
Thus, assuming all the PMOS transistors MP
1
, MP
2
, MP
3
, MP
4
to have the same threshold voltage value Vth′, the minimum high voltage value for proper operation of the voltage shifter
1
is:
VDDHIGH
min=2
*Vth′+VREF
  (2)
Because of this restriction on the high voltage value that can be used for powering it, a voltage shifter
1
as described hereinabove cannot be used for a simple decoupling stage, or buffer stage, in order to apply the low voltage value VDDLOW directly to the source terminals of the transistors MP
1
and MP
2
, when this value VDDLOW is smaller than 2*Vth+VREF.
In practice, however, low voltage values VDDLOW in this “forbidden” range are a common occurrence in applications of submicron CMOS technology.
Until now, no voltage shifter exits that can be operated at voltage values higher than or equal to, in absolute value, the input voltage values, even when this input voltage drops below a limiting value, at no risk for the integrity of the MOS transistors contained in the shifter during operation on a high voltage supply. Also until now, no voltage shifter exist that requires no additional external signals.
SUMMARY OF THE INVENTION
Embodiments of the invention of have the value of an internally generated reference voltage VREF adjusted to suit the value of the higher voltage, VDDHIGH. In particular, the value of the reference voltage VREF will be reduced as the value of the voltage VDDHIGH decreases.
Presented is a CMOS voltage shifter including differential cell circuit portion coupled between a first and a second supply voltage reference, and including a first pair of transistors coupled in a cascode configuration. The voltage shifter uses both a first voltage divider and a second voltage divider. The first voltage divider generates a reference voltage value on a first internal circuit node that is coupled to gate terminals of the first pair of transistors, while the second voltage divider generates another reference voltage value applied to the first internal circuit node when necessary, based on the voltage VDDHIGH.
Also presented is a method of shifting a voltage in a memory circuit supplied with a high voltage supply and a reference voltage supply. The method includes alternatively selecting as an output signal of the voltage shifter either a ground voltage or a voltage generated through a core of the voltage shifter. If the generated voltage is selected as the output signal, the method generates the output voltage by applying a reference voltage generated by a first voltage divider to a set of gates of transistors in the core of the voltage shifter. If a low voltage value on the high voltage supply prevents the voltage shifter from generating the second voltage, the method generates a second reference voltage from a second voltage divider and applies the second reference voltage to the set of gates of the core transistors.
The features and advantages of a voltage shifter according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


REFERENCES:
patent: 5818257 (1998-10-01), Villa
patent: 6064227 (2000-05-01), Saito

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