CMOS voltage reference with a nulling amplifier

Details CMOS voltage reference with a nulling amplifier CMOS voltage reference with a nulling amplifier

1999-10-13

2001-03-13

Wong, Peter S. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000

Reexamination Certificate

active

06201379

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of CMOS voltage references, and more particularly to a CMOS voltage reference having offset nullification.
2. Description of the Related Art
Use of a CMOS process to make a voltage reference can have advantages in cost over a precision-trimmed bipolar process. Problems with the accuracy and stability of CMOS devices must be overcome, however, in order to make a CMOS reference competitive in performance with bipolar references. Specifically, prior art CMOS voltage reference circuits suffer from the following deficiencies:
1) Lack of precision bipolar transistors in which the collector is available. Standard CMOS processes have only substrate PNPs and lateral PNPs. Substrate PNPs have collectors that go only to ground, and have very poor beta values (typically 15). Lateral PNPs have large and unstable offset voltages.
2) Lack of high-value stable and trimmable resistors.
3) Large offsets and low-frequency noise in MOS differential pairs.
4) Limited gain of CMOS amplifier stages.
5) Noise transients from switched-capacitor circuits intended to overcome the limited precision of CMOS devices.
6) Resistance of MOS switches, particularly at low supply voltages, requiring excessively large devices to avoid voltage dependent errors in the final output.
7) Uncorrectable errors in real circuits that do not appear in simulations, making circuit design difficult.
8) Excessive manufacturing complexity which raises the cost.
One of the biggest challenges in designing a precision CMOS voltage reference is overcoming the errors arising from circuitry outside the band-gap core. Unlike the core variations, which tend to be smooth and stable, the outside errors show erratic variations with time and temperature, and cannot be trimmed out. A common technique to avoid the errors arising from mismatches in MOS transistors, for example, uses switched capacitors to sample the offset at the input to a MOS amplifier and subtract it from the signal. Such a technique is disclosed in U.S. Pat. No. 4,190,805, entitled “COMMUTATING AUTOZERO AMPLIFIER” by Bingham. This “autozero” technique is not suitable for precision CMOS voltage references, however, due to the switching transients produced. These transients are too large even with the most careful matching of switches and clock waveforms.
There are many variations on these “autozero” techniques, but every circuit that has switches near the signal path produces transients at the output that are too large for a CMOS voltage reference that must compete with bipolar circuits. The same problem occurs in voltage reference circuits that use switched capacitors in place of precision core resistors, such as the circuit disclosed in U.S. Pat. No. 5,563,504 entitled “SWITCHING BANDGAP VOLTAGE REFERENCE.”
Thus, there is a need to provide a technique for reducing the untrimmable instabilities in the output voltage of a CMOS voltage reference, without introducing other problems, such as switch transients in the output voltage.
SUMMARY OF THE INVENTION
The present invention is a CMOS voltage reference comprising a band-gap core, a primary amplifier and a “nulling” amplifier. An auto-zeroed nulling amplifier is placed outside of the signal path of the primary amplifier, and is used to null the offsets and noise associated with the primary amplifier. The nulling amplifier integrates the offset seen at the input of the primary amplifier, and applies a correction signal to adjust the offset to zero. This correction signal is used for only a relatively slow adjustment of the offset of the primary amplifier. Whatever switch transients occur in the nulling amplifier are effectively filtered out by the long integration time of the nulling amplifier.
The voltage reference may also include slope, level and curvature trim circuits to provide a low-cost CMOS voltage reference that can be trimmed after final packaging. Due to the nulling of the errors elsewhere in the circuit, the trim circuits are able to adjust the variations solely from the band-gap core. Thus, the nulling amplifier facilitates the trimming scheme as well.
Unique elements of the present circuit include independent adjustment of level, slope, and curvature in the voltage vs. temperature characteristic, use of a nulling amplifier to make the temperature characteristic smooth and stable, using on-chip non-volatile memory, and unique circuit techniques to accomplish the trim adjustments while maintaining a high level of precision and stability. Because these adjustments are made by programming a non-volatile memory after final assembly, this circuit does not suffer from the post-trim assembly shifts that often limit the accuracy of bipolar references. The present invention also uses a novel current replication technique in the slope and level trim DACs, and at least one non-linear resistor with optimal curvature to correct high-order curvature in the output.


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