CMOS voltage reference and buffer circuit

Details CMOS voltage reference and buffer circuit CMOS voltage reference and buffer circuit

1989-02-08

1990-09-04

Wong, Peter S.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

3072961, 3072966, 3072967, 330253, 330257, 330260, G05F 330

Patent

active

049547690

ABSTRACT:
A stable, low noise, low output impedance CMOS reference voltage circuit includes a CMOS/bipolar band gap circuit producing a reference voltage on the source of a source follower transistor driven by an output of a CMOS differential amplifier which maintains a V.sub.THERMAL voltage across the bases of a pair of emitter follower transistors driving the inputs of the CMOS differential amplifier. A power supply noise rejection circuit includes a cascode MOSFET coupling the drain of the source follower output transistor to a positive power supply voltage conductor. A current mirror circuit greatly attenuates any power supply voltage perturbations before they reach the gate of the cascode MOSFET. A unity gain buffer includes a CMOS differential amplifier input stage with one input coupled to the output of the source follower transistor and an output driving a CMOS operational transconductance amplifier.

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patent: 4797577 (1989-01-01), Hing
patent: 4808908 (1989-02-01), Lewis et al.

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