CMOS voltage reference

Details CMOS voltage reference CMOS voltage reference

2001-03-29

2002-08-27

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06441680

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a voltage reference, and in particular to a voltage reference that can be implemented in CMOS technology and with good temperature stability.
BACKGROUND OF THE INVENTION
Being able to provide a voltage reference is important in many analog circuits such as linear regulators and data converters. The specifications of the voltage reference, including the temperature coefficient (TC), line regulation (LR) and noise all directly affect the performance of the circuit in which the voltage reference is incorporated. Common ways of providing a voltage reference include bipolar junction transistors, zener diodes, and JFET or depletion-mode NMOS transistors.
Difficulties arise, however, in implementing conventional voltage reference designs in CMOS technology. CMOS technology is popular in circuit design because of the relatively low fabrication costs and short turn-around periods involved. It is therefore strongly desirable to be able to implement a complete circuit, including any necessary voltage reference in CMOS technology.
PRIOR ART
In an attempt to implement a voltage reference in a CMOS environment it is known to use vertical bipolar junction transistors in p- or n-well and p- or n-MOS transistors operating in the weak inversion region to implement a bandgap reference voltage. An example of such a prior art proposal is shown in FIG.
1
. In this design the voltage reference V
ref
=V
be
(of Q
3
(
1
))+IR
2
. The base-emitter voltage of Q
3
(
1
) has a temperature dependency such that it decreases with temperature, while the current I generated by the current mirror has the property of increasing with temperature and thus IR
2
also increases with temperature. Because the two components of the voltage reference have opposite temperature dependencies, by combining them a temperature independent voltage reference may be obtained. A disadvantage of such designs, however, is that trimming is required in the fabrication process and which substantially increases the fabrication costs.
U.S. Pat. No. 5,434534 (Lucas) describes a voltage reference circuit in which the threshold voltages of a p-type and of a n-type CMOS transistor are summed to provide a relatively temperature stable reference voltage. However this design is not completely satisfactory for a number of reasons. Firstly the temperature dependence of a p-type and an n-type CMOS transistor varies for different technologies and in general the dependence of p-type and n-type CMOS transistors are not the same. Thus summing the two voltages without any weighting cannot always provide a complete temperature compensated reference voltage. Furthermore, the circuit of Lucas sums the threshold voltages of p- and n-type CMOS transistors, which implies that a higher supply voltage is required.
SUMMARY OF THE INVENTION
According to the present invention there is provided a circuit for generating a reference voltage comprising a p-type CMOS transistor and an n-type CMOS transistor, said CMOS transistors being operated in the saturation region, and wherein the reference voltage is obtained from the difference between the gate-source voltage of the p- and n-type CMOS transistors with a gain factor greater than or less than 1 being applied to the gate-source voltage of either the p- or n-type CMOS transistor such that the reference voltage is given by the equation: V
ref
=k
1
·V
GSn
−k
2
·|V
GSp
| where either k
1
or k
2
is the gain factor and the other is unity.
It will be understood that depending on the materials used for the two CMOS transistors and their structure, either the p-type or the n-type transistor may have the greater temperature dependence. For applications where the p-type transistor has a greater temperature dependence the general equation may be implemented with either (1) k
1
>1, k
2
=1, or (2) k
1
=1, k
2
<1.
In a first embodiment of the invention (1) is implemented and the gain factor is applied to the gate-source voltage of the n-type transistor. In this embodiment the circuit may implement the equation:
V
ref
=
(
1
+
R
1
R
2
)
·
V
GSn
-
&LeftBracketingBar;
V
GSp
&RightBracketingBar;
where V
ref
is the reference voltage, V
GSn
and V
GSp
are respectively the gate-source voltages of the n- and p-type CMOS transistors, and R
1
and R
2
are respectively first and second resistors connected respectively between the gate of the n-type transistor and the source of the p-type transistor (R
1
), and between ground and the gate of the n-type transistor (R
2
).
In this embodiment the values of R
1
and R
2
are set so as to minimise the temperature coefficient coefficient of the reference voltage circuit. In particular R
1
and R
2
are selected such that
R
1
R
2
=
β
vthp
β
vthn
-
1
where &bgr;
vthn
and &bgr;
vthp
are the temperature coefficients of the threshold voltages of the n- and p-type CMOS transistors respectively. Furthermore, the temperature coefficient of the circuit is minimised by adjusting the transistor size ratio of the CMOS transistors such that
(
W
L
)
p
(
W
L
)
n
=
μ
n
⁢
(
T
o
)
μ
p
⁢
(
T
o
)
⁢
(
T
r
T
o
)
β
μ
⁢
 
⁢
p
-
β
μ
⁢
 
⁢
n
(
1
+
R
1
R
2
)
2
⁢
(
1
2
+
β
μ
⁢
 
⁢
n
2
⁢
β
μ
⁢
 
⁢
p
)
2
where
(i)
(
W
L
)
p
⁢
 
⁢
and
⁢
 
⁢
(
W
L
)
n
 are the channel width to channel length ratio of p-type and n-type CMOS transistors.
(ii) &mgr;
p
(T
o
) and &mgr;
n
(T
o
) are the mobilities of p-type and n-type CMOS transistors at temperature T
o
=0° C.
(iii) &bgr;
&mgr;p
and &bgr;
&mgr;n
are the mobility exponents of p-type and n-type CMOS transistors.
(iv) T
r
is the reference temperature which is set to have zero temperature coefficient.
In a second embodiment of the invention (2) is implemented and the gain factor is applied to the gate-source voltage of the p-type transistor. In this embodiment the circuit implements the equation
V
ref
=
V
GSn
-
(
R
2
R
1
+
R
2
)
·
&LeftBracketingBar;
V
GSp
&RightBracketingBar;
where V
ref
is the reference voltage, V
GSn
and V
GSp
are respectively the gate-source voltages of the n and p-type CMOS transistors, and R
1
and R
2
are respectively first and second resistors where R
1
is connected between the source of the p-type transistor and the gate of the n-type transistor, and R
2
is connected between the gate of the n-type transistor and the gate of the p-type transistor, and wherein the reference voltage is taken from the junction of the gate and the drain of the p-type transistor. As in the first embodiment of the invention, the temperature dependence of the circuit can be minimised by setting the resistor ratio, and the transistor size ratio.
For applications where the n-type transistor has a greater temperature dependence, the general equation may be implemented with either (3) k
1
<1, k
2
=1, or (4) k
1
=1, k
2
>1.
In a third embodiment of the invention (3) is implemented and the circuit implements the equation
V
ref
=
(
R
2
R
1
+
R
2
)
·
V
GSn
-
&LeftBracketingBar;
V
GSp
&RightBracketingBar;
.
In a fourth embodiment of the invention (4) is implemented and the circuit implements the equation
V
ref
=
V
GSn
-
(
1
+
R
1
R
2
)
·
&LeftBracketingBar;
V
GSp
&RightBracketingBar;
.
In both of these embodiments the temperature dependence of the circuit can again be minimised by adjusting the resistor ratio and the transistor size ratio.
In both of these embodiments the temperature dependence of the circuit can again be minimised by adjusting the resistor ratio and the transistor size ratio.


REFERENCES:
patent: 5434534 (1995-07-01), Lucas
patent: 5982201 (1999-11-01), Brokaw et al.
patent: 6040735 (2000-03-01), Park et al.
patent: 6236249 (2001-05-01), Choi et al.
patent: 6316990 (2001-11-01), Tanizawa
Annema, Anne-Johan, “Low-Power Bandgap References Featuring DTMOST's”, IEEE Journal of Solid-State Circuits, vol. 34, No. 7, Jul. 1999, pp. 949-955.
Banba,

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